PCF8562TTSLASH2 datasheet(17/36 Pages) NXP

17 / 36 page

PCF8562_4

Product data sheet

Rev. 04 — 18 March 2009

17 of 36

NXP Semiconductors

PCF8562

Universal LCD driver for low multiplex rates

7.11 Data pointer

The addressing mechanism for the display RAM is realized using the data pointer.

This allows the loading of an individual display data byte, or a series of display data bytes,

into any location of the display RAM. The sequence commences with the initialization of

the data pointer by the load-data-pointer command (see Section 7.17).

Following this command, an arriving data byte is stored at the display RAM address

indicated by the data pointer. The ﬁlling order shown in Figure 10.

After each byte is stored, the contents of the data pointer is automatically incremented by

a value dependent on the selected LCD drive mode:

• In static drive mode by eight

• In 1:2 multiplex drive mode by four

• In 1:3 multiplex drive mode by three

• In 1:4 multiplex drive mode by two

If an I2C-bus data access is terminated early then the state of the data pointer is unknown.

The data pointer should be re-written prior to further RAM accesses.

7.12 Subaddress counter

The storage of display data is determined by the contents of the subaddress counter.

Storage is allowed to take place only when the contents of the subaddress counter agree

with the hardware subaddress applied to A0, A1 and A2. The subaddress counter value is

deﬁned by the device-select command (see Section 7.17). If the contents of the

subaddress counter and the hardware subaddress do not agree then data storage is

inhibited but the data pointer is incremented as if data storage had taken place. The

subaddress counter is also incremented when the data pointer overﬂows.

The hardware subaddress must not be changed while the device is being accessed on the

I2C-bus interface.

7.13 Output bank selector

The output bank selector selects one of the four rows per display RAM address for

transfer to the display register. The actual row selected depends on the particular LCD

drive mode in operation and on the instant in the multiplex sequence.

• In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by

the contents of row 1, row 2 and then row 3.

• In 1:3 multiplex mode, row 0, 1 and 2 are selected sequentially

• In 1:2 multiplex mode, row 0 and 1 are selected

• In static mode, row 0 is selected

The PCF8562 includes a RAM bank switching feature in the static and 1:2 drive modes. In

the static drive mode, the bank-select command (see Section 7.17) may request the

contents of row 2 to be selected for display instead of the contents of row 0. In 1:2 mode,

the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the

provision for preparing display information in an alternative bank and to be able to switch

to it once it is assembled.

PCF8562TT/2 датащи(PDF) 17 Page - NXP Semiconductors

PCF8562TT/2 датащи(HTML) 17 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

датащи скачать

ссылки URL