WM8148 datasheet(35/43 Pages) WOLFSON

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WM8148

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 4.0 April 1999

CONTROL

BIT/WORD

DEFAULT

DESCRIPTION

Set-up Register 2

Address

000010

SENBL[7:0]

b7…..b0

0000

Selective power enable register, activated when SELEN = 1 (Set-up Register 1).

Each bit activates respective cell when 1, de-activates when 0.

SENBL[0]

Bandgap/Bias

SENBL[1]

VRT, VRB buffers

SENBL[2]

VRX buffer

SENBL[3]

RLC DAC (allows VRLC to be externally driven)

SENBL[4]

Red S/H, PGA

SENBL[5]

Green S/H, PGA

SENBL[6]

Blue S/H, PGA

SENBL[7]

ADC

Set-up Register 3

Address

000011

RESREF[3:0]

b3, b2, b1, b0

0110

Selects the position of either the reset sample and the clamp points in CDS modes,

or the position of just the clamp pulse in non-CDS modes. See Mode Descriptions for

further details.

FREE

Enables internal clocks to be free running, without VSMP pulse input.

FREE

Requires continuous VSMP pulse input every N periods of MCLK

Free running

SMALL

Reduces video and reset sample pulse widths by half an MCLK period.

SMALL

Default pulse widths

Reduces pulse widths

CHAN[1:0]

b7, b6

Selects the input channel in One-channel (line by line) modes.

No effect when not in One-channel mode.

CHAN[1]

CHAN[0]

Red channel

Green channel

Blue channel

Reserved

Software Reset

Address

000100

SRES[1:0]

b1, b0

Writing to this register causes a software reset. There a three types of reset available:

SRES[1]

SRES[0]

Same action as NRESET pin

Resets all registers to default including RLCEXT.

(Except EN, SELEN and SENBL[7:0], which are

not changed)

Resets PGA and DAC only (X denotes either 1 or 0)

Setup Register 4

Address

000101

DEL[1:0]

b1, b0

Adjusts the latency through the device in ADC clock periods.

See Detailed Mode Timing Diagrams for details.

FDEL[1:0]

b3, b2

Adjusts the latency through the device in half-MCLK increments.

FDEL[1]

FDEL[0]

Default position

Earlier by MCLK/2

Later by MCLK/2

Invalid in modes 0, 1, 4 and 5

Later by MCLK/2

Invalid in modes 0, 1, 4 and 5

In these invalid modes, output data is held constant, TVIOL is not flagged.

VSMPOP

Enables output of internally generated MCLK/N sync pulse (only if FREE also set).

VSMPOP

Requires external VSMP

VSMP pin becomes sync output

Reserved for Wolfson use only, must be programmed to 0.

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