WM8148 datasheet(19/43 Pages) WOLFSON

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WM8148

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 4.0 April 1999

DIFFERENTIAL

SIGNAL RANGE

VIDEO SIGNAL

TYPE

BLACK

WHITE

PGAFS[1:0]

OUTPUT CODE

INVOP = 0

OUTPUT CODE

INVOP = 1

Positive-going,

e.g. many CIS

Black = 0

White = 4095

Black = 4095

White = 0

Negative-going,

e.g. CCDs

-3V

Black = 4095

White = 0

Black = 0

White = 4095

Bipolar

-1.5V

+1.5V

00, 01

Black = 0

White = 4095

Black = 4095

White = 0

Table 2 PGAFS[1:0] Setting for Video Signal Types

If the signal exceeds the chosen range, it is clipped and the error flag OVRNG is set, which may be

output via the SDO or OP pins.

OVERALL SIGNAL FLOW SUMMARY

Figure 20 represents the processing of the video signal through the WM8148.

The INPUT SAMPLING BLOCK produces an effective input voltage V1. For CDS, this is the

difference between the input video level VIN and the input reset level VRESET. For non-CDS this is the

difference between the input video level VIN and the voltage on the VRLC pin, VVRLC, optionally set via

the RLC DAC.

The OFFSET DAC BLOCK then adds the amount of fine offset adjustment required to move the

black level of the input signal towards 0V, producing V2.

The PGA BLOCK then amplifies the white level of the input signal to maximise the ADC range,

outputting voltage V3.

The ADC BLOCK then converts the analogue signal, V3, to a 12-bit unsigned digital output, D1.

The digital output is then inverted if required, through the OUTPUT INVERT BLOCK to produce D2.

RESET

VRLC

MODE[0] = 0

MODE[0] = 1

RLCEXT=1

200mV*(DAC[7:0]-127.5)/127.5

analog

AVDD*RLCV[3:0]/15

OP[11:0]

digital

ADC BLOCK

PGA

BLOCK

OFFSET DAC

BLOCK

INPUT

SAMPLING

BLOCK

MODE[0], RLCEXT,RLCV[3:0], DAC[7:0],

PGA[5:0], PGAFS[1:0] and INVOP are set

by programming internal control registers.

MODE[0]=0 for CDS, 1 for non-CDS

IN is RINP or GINP or BINP

RESET is V IN sampled during reset clamp

VRLC is voltage applied to VRLC pin

PGA gain

A = 52/(70-PGA[5:0])

OUTPUT

INVERT

BLOCK

D2 = D1 if INVOP = 0

D2 =4095-D1 if INVOP = 1

Offset

DAC

RLC

DAC

RLCEXT=0

3 x 4095/V FS) =

+0 codes if PGAFS[1:0]=11

+4095 codes if PGAFS[1:0]=10

+2047 codes if PGAFS[1:0]=0x

Figure 20 Overall Signal Flow

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