WM8148 datasheet(18/43 Pages) WOLFSON

18 / 43 page

WM8148

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 4.0 April 1999

If pin RLC is tied high then reset level clamping is applied on every pixel. Alternatively, for line-by-

line clamping, pin RLC can be driven high at the start of a line (during the dummy black pixel output),

then driven low for the remainder of the line. If pin RLC is tied low then reset level clamping will not be

applied.

The VRLC voltage, to which the reset level is clamped, can be defined either by an external voltage

or internally via the 4-bit programmable RLC DAC. To clamp to an internally defined voltage RLCEXT

must be set to ‘0’. Control bits RLCV[3:0] then program the RLC DAC to a voltage ranging between

0V and AVDD linearly over 15 steps. The voltage from the RLC DAC will also be presented on pin

VRLC which should be decoupled to analogue ground. Alternatively, by setting control bit RLCEXT to

‘1’, the RLC DAC is disconnected and the VRLC pin is driven externally to any voltage between 0V

and AVDD.

PROGRAMMABLE OFFSET DAC

The output from the Input Sampling Block is added to the output of an 8-bit Offset DAC to allow

cancellation of offsets in sensor black level and input offsets of the WM8148. The DACs cover a

range of

±200mV in 255 equal steps of 1.57mV, programmable via the DMI. Programming 00(hex) to

the DAC gives an offset adjustment of -200mV, FF(hex) adjusts the input signal by +200mV.

PROGRAMMABLE GAIN AMPLIFIERS (PGA)

When the black level has been adjusted using the Offset DAC, the gain of the PGA can be

programmed to amplify the white level signal to cover the full ADC range (3V). Figure 18 shows a

graph of the PGA gain response. This gain curve is non-linear, with gain given by:

Gain = 52 / {70 – PGA[5:0](dec)}

This gives a gain ranging from 0.74 times to 7.4 times over 63 steps, with minimum gain

corresponding to 00(hex) and maximum gain corresponding to 3F(hex). Figure 19 shows the PGA

gain code settings required, for PGA input voltages from 0.4V to 4.0V, to produce a PGA output

equivalent to the full scale input range of the ADC (3V).

PGA Gain code, PGA[5:0] (hex)

Figure 18 PGA Gain Response

Figure 19 PGA Input vs Gain Code for Full Scale ADC Input

ANALOGUE TO DIGITAL CONVERTER (ADC)

The output of the PGA is applied to a high performance ADC. The differential signal from the PGA

ranges from 0V (black level) to either +3V or -3V (white level), depending on the polarity of the input

signal to the device. Control bits PGAFS[1:0] are used to configure the input of the ADC to accept the

desired input signal range. This is achieved by adding 0, + or - half of the full scale voltage to the

ADC input signal on a channel-by-channel basis, as shown in the block diagram on page 1. Table 2

shows the PGAFS[1:0] settings required for different video signal types.

WM8148 датащи(PDF) 18 Page - Wolfson Microelectronics plc