WM8148 datasheet(23/43 Pages) WOLFSON

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WM8148

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 4.0 April 1999

STB

DNA

RNW

OP[11:4]

Address

Hi-Z

Driven by WM8148

Driven Externally

Hi-Z

Normal Output Data

Read Data

Driven by WM8148

Normal Output Data

Figure 25 Parallel Interface Register Read-back

pulsing the STB pin low. Note that a4 = 1 and pins RNW and DNA are low. When RNW and DNA are

high and STB is strobed again, the contents (d7, d6, d5, d4, d3, d2, d1, d0) of the corresponding

the current contents of the ADC (shown as Normal Output Data) will be present on OP[11:4].

OUTPUT ENABLE

When high, pin OEB makes pins OP[11:0] Hi-Z regardless of other pin settings. Therefore when the

WM8148 is outputting normal ADC data, or during register read, pin OEB must be set to ‘0’. During

Table 4 shows the state of pins OP[11:0] for possible settings of OEB, RNW and STB.

OEB

RNW

STB

OP[11:0]

Hi-Z

Read register data

Read ADC data

Table 4 State of OP[11:0] During Register Read/Write

POWER MANAGEMENT

Power management for the WM8148 is performed via the DMI. The device can be powered on or off

completely by the control bit EN. Alternatively, when control bit SELEN is high, only blocks selected

by further control bits SENBL[7:0] are powered up. This allows the user to optimise power dissipation

in certain modes, or to define intermediate standby modes to allow a quicker recovery into a fully

active state.

SELEN

Device completely powers down.

Device completely powers up.

Only blocks with respective SENBL bit high

go/remain active.

Table 5 Power Down control

Control bit RLCEXT is used to disable the RLC DAC, regardless of EN or SENBL[7:0]. If this option is

taken, pin VRLC can be driven externally for reset level clamping.

One-channel and Two-channel sampling modes do not automatically power down unused PGAs, the

appropriate SENBL bits should be set during initialisation to save power. The WM8148 will still

operate normally if the unused blocks are not powered down.

All the internal registers maintain their previously programmed value in power down modes, and the

DMI inputs remain active.

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