WM8148 datasheet(22/43 Pages) WOLFSON

22 / 43 page

WM8148

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 4.0 April 1999

Figure 22 shows register writing in serial mode. Three pins, SCK, SDI and SEN are used. A six-bit

address (a5, 0, a3, a2, a1, a0) is clocked in through SDI, MSB first, followed by an eight-bit data word

(b7, b6, b5, b4, b3, b2, b1, b0), also MSB first. Each bit is latched on the rising edge of SCK. When

the data has been shifted into the device, a pulse is applied to SEN to transfer the data

to the appropriate internal register. Note all valid registers have address bit a4 equal to 0 in

write mode.

SCK

SEN

SDI

a 5

a 3 a 2 a 1 a 0

xxxx

xxx

Address

Data Word

d7 d6 d5 d4 d3 d2 d1 d0

Output Data Word

SDO

OEB

Figure 23 Serial Interface Register Read-back

1, followed by an 8-bit dummy data word. Writing address (a5, 1, a3, a2, a1, a0) will cause the

contents (d7, d6, d5, d4, d3, d2, d1, d0) of corresponding register (a5, 0, a3, a2, a1, a0) to be output

MSB first on pin SDO (on the falling edge of SCK), provided control bits SDO[1:0] = 00. If SDO[1:0] is

not set to 00 then error flags will be output instead of the register contents. Note that if SDI and SDO

are not connected together, the next word may be read in to SDI while the previous word is still being

output on SDO. Alternatively, the user may tie the SDI and SDO pins together to make a 3-wire serial

interface. The user must ensure that the circuit driving SDI is Hi-Z while the SDO pin is active.

Pin OEB must be low to enable the output data word to be output.

PARALLEL INTERFACE

STB

DNA

RNW

OP[11:4]

Address

Data

Hi-Z

Driven by WM8148

Driven Externally

Normal Output Data

Driven by WM8148

Normal Output Data

Figure 24 Parallel Interface Register Write

The parallel interface uses bits [11:4] of the OP bus and the STB, DNA and RNW pins. Pin RNW

must be low during a write operation. The DNA pin defines whether the data byte is address (low) or

data (high). The 6-bit address (a5, 0, a3, a2, a1, a0) is input into OP[9:4], LSB into OP[4], (OP[10]

and OP[11] are ignored) when DNA is low, then the 8-bit data word is input into OP[11:4], LSB into

OP[4], when DNA is high. The data bus OP[11:4] for both address and data is latched in during the

low period of STB. Note all valid registers have address bit a4 equal to 0.

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