HT95R64 datasheet(38/82 Pages) HOLTEK

38 / 82 page

HT95R64/HT95R65

Rev. 1.00

March 3, 2010

· SRW Bit

The SRW bit in the SIMCTL1 register defines whether

the microcontroller slave device wishes to read data

from the I

2C bus or write data to the I2C bus. The

microcontroller should examine this bit to determine if

it is to be a transmitter or a receiver. If the SRW bit is

set to

²1² then this indicates that the master wishes to

read data from the I

2 C bus, therefore the

microcontroller slave device must be setup to send

data to the I

2C bus as a transmitter. If the SRW bit is

²0² then this indicates that the master wishes to send

data to the I

2C bus, therefore the microcontroller slave

device must be setup to read data from the I

2C bus as

a receiver.

· Acknowledge Bit

After the master has transmitted a calling address,

any slave device on the I

2C bus, whose own internal

address matches the calling address, must generate

an acknowledge signal. This acknowledge signal will

inform the master that a slave device has accepted its

calling address. If no acknowledge signal is received

by the master then a STOP signal must be transmitted

by the master to end the communication. When the

HAAS bit is high, the addresses have matched and

the microcontroller slave device must check the SRW

bit to determine if it is to be a transmitter or a receiver.

If the SRW bit is high, the microcontroller slave device

should be setup to be a transmitter so the HTX bit in

the SIMCTL1 register should be set to

²1² if the SRW

bit is low then the microcontroller slave device should

be setup as a receiver and the HTX bit in the SIMCTL1

²0².

· Data Byte

The transmitted data is 8-bits wide and is transmitted

after the slave device has acknowledged receipt of its

slave address. The order of serial bit transmission is

the MSB first and the LSB last. After receipt of 8-bits of

data, the receiver must transmit an acknowledge sig-

nal, level

²0², before it can receive the next data byte.

If the transmitter does not receive an acknowledge bit

signal from the receiver, then it will release the SDA

line and the master will send out a STOP signal to re-

lease control of the I

2C bus. The corresponding data

will be stored in the SIMDR register. If setup as a

transmitter, the microcontroller slave device must first

write the data to be transmitted into the SIMDR regis-

ter. If setup as a receiver, the microcontroller slave de-

vice must read the transmitted data from the SIMDR

· Receive Acknowledge Bit

When the receiver wishes to continue to receive the

next data byte, it must generate an acknowledge bit,

known as TXAK, on the 9th clock. The microcontroller

slave device, which is setup as a transmitter will check

the RXAK bit in the SIMCTL1 register to determine if it

is to send another data byte, if not then it will release

the SDA line and await the receipt of a STOP signal

from the master.

Peripheral Clock Output

The Peripheral Clock Output allows the device to supply

external hardware with a clock signal synchronised to

the microcontroller clock.

Peripheral Clock Operation

As the peripheral clock output pin, PCLK, is shared with

an I/O pin, the required pin function is chosen via

PCKEN in the SIMCTL0 register. The Peripheral Clock

function is controlled using the SIMCTL0 register. The

clock source for the Peripheral Clock Output can origi-

nate from either the Timer 2 divided by two or a divided

ratio of the internal fSYS clock. The PCKEN bit in the

SIMCTL0 register is the overall on/off control, setting the

bit high enables the Peripheral Clock, clearing it dis-

ables it. The required division ratio of the system clock is

selected using the PCKPSC0 and PCKPSC1 bits in the

same register. If the system enters the Sleep Mode this

will disable the Peripheral Clock output.

S C L

S D A

S t a r t b i t

D a t a

s t a b l e

D a t a

a l l o w

c h a n g e

S t o p b i t

Data Timing Diagram

f S Y S

T i m e r 2 ¸ 2

P C L K

o r P E 4

S e l e c t

P C L K

o r

P E 4

¸ 1 , 4 , 8

P C K E N

P C K P S C 0

P C K P S C 1

S l e e p M o d e

Peripheral Clock Block Diagram

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