HT95R64 datasheet(25/82 Pages) HOLTEK

25 / 82 page

HT95R64/HT95R65

Rev. 1.00

March 3, 2010

Timer/Event Counter will reload the value already

loaded into the preload register and continue counting.

The interrupt can be disabled by ensuring that the

Timer/Event Counter Interrupt Enable bit in the Interrupt

Control Register, is reset to zero.

To ensure that the timer pin is configured to operate as

an event counter input pin the Timer Control Register

must place the Timer/Event Counter in the Event

Counting Mode. It should be noted that in the event

counting mode, even if the microcontroller is in the

Power Down Mode, the Timer/Event Counter will con-

tinue to record externally changing logic events on the

timer input pin. As a result when the timer overflows it

will generate a timer interrupt and corresponding

wake-up source.

Configuring the Pulse Width Measurement Mode

In this mode, the Timer/Event Counter can be utilised to

measure the width of external pulses applied to the ex-

ternal timer pin. To operate in this mode, the Operating

Mode Select bit pair in the Timer Control Register must

be set to the correct value as shown.

Control Register Operating Mode

Select Bits for the Pulse Width

Measurement Mode

Bit7 Bit6

In this mode the internal clock is used as the

Timer/Event Counter clock. After the other bits in the

Timer Control Register have been setup, the enable bit,

which is bit 4 of the Timer Control Register, can be set

high to enable the Timer/Event Counter, however it will

not actually start counting until an active edge is re-

ceived on the external timer pin.

If the Active Edge Select bit, which is bit 3 of the Timer

Control Register, is low, once a high to low transition has

been received on the external timer pin, the Timer/Event

Counter will start counting until the external timer pin re-

turns to its original high level. At this point the enable bit

will be automatically reset to zero and the Timer/Event

Counter will stop counting. If the Active Edge Select bit

is high, the Timer/Event Counter will begin counting

once a low to high transition has been received on the

external timer pin and stop counting when the external

timer pin returns to its original low level. As before, the

enable bit will be automatically reset to zero and the

T M R 2 C R e g i s t e r

b 7

T 2 O N

T 2 M 0

T 2 M 1

b 0

T 2 M 1

T 2 M 0

n o m o d e a v a i l a b l e

t i m e r m o d e

n o m o d e a v a i l a b l e

N o t i m p l e m e n t e d , r e a d a s " 0 "

T i m e r / E v e n t C o u n t e r C o u n t i n g E n a b l e

1 : e n a b l e

0 : d i s a b l e

N o t i m p l e m e n t e d , r e a d a s " 0 "

O p e r a t i n g M o d e S e l e c t

Timer2 Control Register

T M R 1 C R e g i s t e r

N o t i m p l e m e n t e d , r e a d a s " 0 "

b 7

E v e n t C o u n t e r A c t i v e E d g e S e l e c t

1 : c o u n t o n f a l l i n g e d g e

0 : c o u n t o n r i s i n g e d g e

T 1 E

T 1 O N

T 1 M 0

T 1 M 1

b 0

T i m e r / E v e n t C o u n t e r C o u n t i n g E n a b l e

1 : e n a b l e

0 : d i s a b l e

O p e r a t i n g M o d e S e l e c t

T 1 M 1

T 1 M 0

n o m o d e a v a i l a b l e

e v e n t c o u n t e r m o d e

t i m e r m o d e

p u l s e w i d t h m e a s u r e m e n t m o d e

P u l s e W i d t h M e a s u r e m e n t A c t i v e E d g e S e l e c t

1 : s t a r t c o u n t i n g o n r i s i n g e d g e , s t o p o n f a l l i n g e d g e

0 : s t a r t c o u n t i n g o n f a l l i n g e d g e , s t o p o n r i s i n g e d g e

N o t i m p l e m e n t e d , r e a d a s " 0 "

Timer/Event Counter 1 Control Register

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