HT95R64 datasheet(31/82 Pages) HOLTEK

31 / 82 page

HT95R64/HT95R65

Rev. 1.00

March 3, 2010

The SIMDR register is used to store the data being

transmitted and received. The same register is used by

both the SPI and I

2 C functions. Before the

microcontroller writes data to the SPI bus, the actual

data to be transmitted must be placed in the SIMDR reg-

ister. After the data is received from the SPI bus, the

microcontroller can read it from the SIMDRregister. Any

transmission or reception of data from the SPI bus must

be made via the SIMDR register.

Bit

76543210

Label SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0

R/W

R/W R/W R/W R/W R/W R/W R/W R/W

POR

XXXXXXXX

There are also two control registers for the SPI inter-

face, SIMCTL0 and SIMCTL2. Note that the SIMCTL2

2C function. The SIMCTL1 register is not used by the

SPI function, only by the I

2C function. Register

SIMCTL0 is used to control the enable/disable function

and to set the data transmission clock frequency. Al-

though not connected with the SPI function, the

SIMCTL0 register is also used to control the Peripheral

Clock prescaler. Register SIMCTL2 is used for other

control functions such as LSB/MSB selection, write colli-

sion flag etc.

The following gives further explanation of each

SIMCTL1 register bit:

· SIMIDLE

The SIMIDLE bit is used to select if the SPI interface

continues running when the device is in the IDLE

mode. Setting the bit high allows the SPI interface to

maintain operation when the device is in the Idle

mode. Clearing the bit to zero disables any SPI opera-

tions when in the Idle mode.

This SPI/I

2C idle mode control bit is located at

CLKMOD register bit4.

· SIMEN

The bit is the overall on/off control for the SPI inter-

face. When the SIMEN bit is cleared to zero to disable

the SPI interface, the SDI, SDO, SCK and SCS lines

will be in a floating condition and the SPI operating

current will be reduced to a minimum value. When the

bit is high the SPI interface is enabled. The SIMconfig-

uration option must have first enabled the SIM inter-

face for this bit to be effective. Note that when the

SIMEN bit changes from low to high the contents of

the SPI control registers will be in an unknown condi-

tion and should therefore be first initialised by the ap-

plication program.

· SIM0~SIM2

These bits setup the overall operating mode of the SIM

function. As well as selecting if the I

2C or SPI function,

they are used to control the SPI Master/Slave selec-

tion and the SPI Master clock frequency. The SPI

clock is a function of the system clock but can also be

chosen to be sourced from the Timer. If the SPI Slave

Mode is selected then the clock will be supplied by an

external Master device.

SIM0 SIM1 SIM2

SPI Master/Slave Clock

Control and I2C Enable

SPI Master, fSYS/4

SPI Master, fSYS/16

SPI Master, fSYS/64

SPI Master, fSUB

SPI Master Timer 2 output/2

SPI Slave

110

2C mode

Not used

SPI Control Register

- SIMCTL2

The SIMCTL2 register is also used by the I

2C interface

but has the name SIMAR.

· TRF

The TRF bit is the Transmit/Receive Complete flag and

is set high automatically when an SPI data transmis-

sion is completed, but must be cleared by the applica-

tion program. It can be used to generate an interrupt.

· WCOL

The WCOL bit is used to detect if a data collision has

occurred. If this bit is high it means that data has been

attempted to be written to the SIMDR register during a

data transfer operation. This writing operation will be

ignored if data is being transferred. The bit can be

cleared by the application program. Note that using

the WCOL bit can be disabled or enabled via configu-

ration option.

· CSEN

The CSEN bit is used as an on/off control for the SCS

pin. If this bit is low then the SCS pin will be disabled

and placed into a floating condition. If the bit is high

the SCS pin will be enabled and used as a select pin.

Note that using the CSEN bit can be disabled or en-

abled via configuration option.

· MLS

This is the data shift select bit and is used to select

how the data is transferred, either MSB or LSB first.

Setting the bit high will select MSB first and low for

LSB first.

· CKEG and CKPOL

These two bits are used to setup the way that the

clock signal outputs and inputs data on the SPI bus.

These two bits must be configured before data trans-

fer is executed otherwise an erroneous clock edge

may be generated. The CKPOL bit determines the

base condition of the clock line, if the bit is high then

the SCK line will be low when the clock is inactive.

When the CKPOL bit is low then the SCK line will be

high when the clock is inactive. The CKEG bit deter-

mines active clock edge type which depends upon the

condition of CKPOL.

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