HT95R64 datasheet(20/82 Pages) HOLTEK

20 / 82 page

HT95R64/HT95R65

Rev. 1.00

March 3, 2010

curs, the programmer should check bit4~bit6 of MFIC0

to determine the cause of the interrupt.

MFIC1 Register

- MFIC1

The SPI/I

2C interrupt, external peripheral interrupt,

timer 2 interrupt are three additional multi-function inter-

rupts. They are enabled or disabled individually by

bit0~2 of MFIC1. When a multi-function interrupt occurs,

the programmer should check bit4~bit6 of MFIC1 to de-

termine the cause of the interrupt.

PFD Registers

- PFDC/PFDD

The device contains a Programmable Frequency Di-

vider function which can generate accurate frequencies

based on the system clock. The clock source, enable

function and output frequency is controlled using these

two registers.

RTCC Register

The device contains a Real Time Clock function other-

wise known as the RTC. To control this function a regis-

ter known as the RTCC register is provided which

provides the overall on/off control and time out flag.

DAC Registers

- VOICEC/VOL/DAL/DAH

These four registers are for 12-bit DAC output data and

volume control.

Low Battery Detect Register

- LBDC

This register is to control the LBD function and to report

the low battery status.

Software COM Register

- SCOMC

The pins PD0~PD3 on Port D can be used as SCOM

lines to drive an external LCD panel. To implement this

function, the SCOMC register is used to setup the cor-

rect bias voltages on these pins.

Input/Output Ports

Holtek microcontrollers offer considerable flexibility on

their I/O ports. With the input or output designation of ev-

ery pin fully under user program control, pull-high options

for all ports and wake-up options on certain pins, the user

is provided with an I/O structure to meet the needs of a

wide range of application possibilities. The device pro-

vides bidirectional input/output lines labeled with port

names PA, PC, PD, PE and PF. These I/O ports are

mapped to the Data Memory with specific addresses as

shown in the Special Purpose Data Memory table. All of

these I/O ports can be used for input and output opera-

tions. For input operation, these ports are non-latching,

which means the inputs must be ready at the T2 rising

edge of instruction

²MOV A,[m]², where m denotes the

port address. For output operation, all the data is latched

and remains unchanged until the output latch is rewritten.

Unlike the other port lines, PC2 and PC3 are NMOS

type output-only lines. They have neither pull high op-

tion nor a port control bit.

Pull-high Resistors

Many product applications require pull-high resistors for

their switch inputs usually requiring the use of an exter-

nal resistor. To eliminate the need for these external re-

sistors, all I/O pins, when configured as an input have

the capability of being connected to an internal pull-high

resistor. These pull-high resistors are selectable via

configuration options and are implemented using a

weak PMOS transistor.

Port A Wake-up

Each device has a HALT instruction enabling the

microcontroller to enter a Power Down Mode and pre-

serve power, a feature that is important for battery and

other low-power applications. Various methods exist to

wake-up the microcontroller, one of which is to change

the logic condition on one of the Port A pins from high to

low. After a

²HALT² instruction forces the microcontroller

into entering the Power Down mode, the device will re-

main idle or in a low-power state until the logic condition

of the selected wake-up pin on Port A changes from high

to low. This function is especially suitable for applica-

tions that can be woken up via external switches. Note

that each pin on Port A can be selected individually to

have this wake-up feature.

I/O Port Control Registers

Each I/O port has its own control register PAC, PCC,

PDC, PEC and PFC, to control the input/output configu-

ration. with this control register, each CMOS output or

input with or without pull-high resistor structures can be

reconfigured dynamically under software control. Each

pin of the I/O ports is directly mapped to a bit in its asso-

ciated port control register. For the I/O pin to function as

an input, the corresponding bit of the control register

must be written as a

²1². This will then allow the logic

state of the input pin to be directly read by instructions.

When the corresponding bit of the control register is

written as a

²0², the I/O pin will be setup as a CMOS out-

put. If the pin is currently setup as an output, instructions

can still be used to read the output register. However, it

should be noted that the program will in fact only read

the status of the output data latch and not the actual

logic status of the output pin.

I/O Pin Structures

The following diagrams illustrate the I/O pin internal

structures. As the exact logical construction of the I/O

pin may differ from these drawings, they are supplied as

a guide only to assist with the functional understanding

of the I/O pins.

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