HT95R64 datasheet(36/82 Pages) HOLTEK

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HT95R64/HT95R65

Rev. 1.00

March 3, 2010

2C Control Register

- SIMAR

The SIMARregister is also used by the SPI interface but

has the name SIMCTL2.

The SIMAR register is the location where the 7-bit slave

address of the microcontroller is stored. Bits 1~7 of the

SIMARregister define the microcontroller slave address.

Bit 0 is not defined. When a master device, which is con-

nected to the I

2C bus, sends out an address, which

matches the slave address in the SIMAR register, the

microcontroller slave device will be selected. Note that

the SIMAR register is the same register as SIMCTL2

which is used by the SPI interface.

2C Bus Communication

Communication on the I

2C bus requires four separate

steps, a START signal, a slave device address transmis-

sion, a data transmission and finally a STOP signal.

When a START signal is placed on the I

2C bus, all de-

vices on the bus will receive this signal and be notified of

the imminent arrival of data on the bus. The first seven

bits of the data will be the slave address with the first bit

being the MSB. If the address of the microcontroller

matches that of the transmitted address, the HAAS bit in

the SIMCTL1 register will be set and an I

2C interrupt will

be generated. After entering the interrupt service rou-

tine, the microcontroller slave device must first check

the condition of the HAAS bit to determine whether the

interrupt source originates from an address match or

from the completion of an 8-bit data transfer. During a

data transfer, note that after the 7-bit slave address has

been transmitted, the following bit, which is the 8th bit, is

the read/write bit whose value will be placed in the SRW

bit. This bit will be checked by the microcontroller to de-

termine whether to go into transmit or receive mode. Be-

fore any transfer of data to or from the I

2C bus, the

microcontroller must initialise the bus, the following are

steps to achieve this:

Step 1

Write the slave address of the microcontroller to the I

bus address register SIMAR.

Step 2

Set the SIMEN bit in the SIMCTL0 register to

²1² to en-

able the I

2C bus.

Step 3

Set the EHI bit of the interrupt control register to enable

the I

2C bus interrupt.

· Start Signal

The START signal can only be generated by the mas-

ter device connected to the I

2C bus and not by the

microcontroller, which is only a slave device. This

START signal will be detected by all devices con-

nected to the I

2C bus. When detected, this indicates

that the I

2C bus is busy and therefore the HBB bit will

be set. A START condition occurs when a high to low

transition on the SDA line takes place when the SCL

line remains high.

· Slave Address

The transmission of a START signal by the master will

be detected by all devices on the I

2C bus. To deter-

mine which slave device the master wishes to com-

municate with, the address of the slave device will be

sent out immediately following the START signal. All

slave devices, after receiving this 7-bit address data,

will compare it with their own 7-bit slave address. If the

address sent out by the master matches the internal

address of the microcontroller slave device, then an

internal I

2C bus interrupt signal will be generated. The

next bit following the address, which is the 8th bit, de-

fines the read/write status and will be saved to the

SRW bit of the SIMCTL1 register. The device will then

transmit an acknowledge bit, which is a low level, as

the 9th bit. The microcontroller slave device will also

set the status flag HAAS when the addresses match.

As an I

2C bus interrupt can come from two sources,

when the program enters the interrupt subroutine, the

HAAS bit should be examined to see whether the in-

terrupt source has come from a matching slave ad-

dress or from the completion of a data byte transfer.

When a slave address is matched, the device must be

placed in either the transmit mode and then write data

to the SIMDR register, or in the receive mode where it

must implement a dummy read from the SIMDR regis-

ter to release the SCL line.

S t a r t

W r i t e S l a v e

A d d r e s s t o S I M A R

S E T S I M [ 2 : 0 ] = 1 1 0

S E T S I M E N

I 2 C B u s

I n t e r r u p t = ?

E n a b l e

D i s a b l e

S E T E H I

W a i t f o r I n t e r r u p t

G o t o M a i n P r o g r a m

C L R E H I

P o l l H I F t o d e c i d e

w h e n t o g o t o I 2 C B u s I S R

G o t o M a i n P r o g r a m

2C Bus Initialisation Flow Chart

S I M A R R e g i s t e r

b 7

N o t i m p l e m e n t e d , r e a d a s " 0 "

I 2 C d e v i c e s l a v e a d d r e s s

b 0

S A 5

S A 4

S A 6

S A 0

S A 3

S A 2

S A 1

2C Slave Address Register

- SIMAR

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