ATmega328P datasheet(216/448 Pages) ATMEL

номер детали	ATmega328P

подробное описание детали	8-bit Microcontroller with 4/8/16/32K Bytes In-System Programmable Flash

PDF	448 Pages

Scroll/Zoom	100%

производитель	ATMEL [ATMEL Corporation]

домашняя страница	http://www.atmel.com

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216 / 448 page

216

8161D–AVR–10/09

ATmega48PA/88PA/168PA/328P

21.3

Data Transfer and Frame Format

21.3.1

Transferring Bits

Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The level

of the data line must be stable when the clock line is high. The only exception to this rule is for

generating start and stop conditions.

Figure 21-2. Data Validity

21.3.2

START and STOP Conditions

The Master initiates and terminates a data transmission. The transmission is initiated when the

Master issues a START condition on the bus, and it is terminated when the Master issues a

STOP condition. Between a START and a STOP condition, the bus is considered busy, and no

other master should try to seize control of the bus. A special case occurs when a new START

condition is issued between a START and STOP condition. This is referred to as a REPEATED

START condition, and is used when the Master wishes to initiate a new transfer without relin-

quishing control of the bus. After a REPEATED START, the bus is considered busy until the next

STOP. This is identical to the START behavior, and therefore START is used to describe both

START and REPEATED START for the remainder of this datasheet, unless otherwise noted. As

depicted below, START and STOP conditions are signalled by changing the level of the SDA

line when the SCL line is high.

Figure 21-3. START, REPEATED START and STOP conditions

SDA

SCL

Data Stable

Data Change

SDA

SCL

START

STOP

REPEATED START

STOP

START

ATmega328P датащи(PDF) 216 Page - ATMEL Corporation