ATmega328P datasheet(99/448 Pages) ATMEL

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8161D–AVR–10/09

ATmega48PA/88PA/168PA/328P

Figure 14-4. Compare Match Output Unit, Schematic

The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform

Generator if either of the COM0x1:0 bits are set. However, the OC0x pin direction (input or out-

put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction

ble on the pin. The port override function is independent of the Waveform Generation mode.

The design of the Output Compare pin logic allows initialization of the OC0x state before the out-

put is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of

operation. See Section “14.9” on page 106.

14.6.1

Compare Output Mode and Waveform Generation

The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes.

For all modes, setting the COM0x1:0 = 0 tells the Waveform Generator that no action on the

OC0x Register is to be performed on the next compare match. For compare output actions in the

non-PWM modes refer to Table 14-2 on page 106. For fast PWM mode, refer to Table 14-3 on

page 106, and for phase correct PWM refer to Table 14-4 on page 107.

A change of the COM0x1:0 bits state will have effect at the first compare match after the bits are

written. For non-PWM modes, the action can be forced to have immediate effect by using the

FOC0x strobe bits.

14.7

Modes of Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is

defined by the combination of the Waveform Generation mode (WGM02:0) and Compare Output

mode (COM0x1:0) bits. The Compare Output mode bits do not affect the counting sequence,

while the Waveform Generation mode bits do. The COM0x1:0 bits control whether the PWM out-

put generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes

the COM0x1:0 bits control whether the output should be set, cleared, or toggled at a compare

match (See Section “14.6” on page 98.).

For detailed timing information refer to ”Timer/Counter Timing Diagrams” on page 104.

PORT

DDR

OCnx

Waveform

Generator

COMnx1

COMnx0

FOCn

clk

I/O

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