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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ATmega169P датащи(PDF) 249 Page - ATMEL Corporation |
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ATmega169P датащи(HTML) 249 Page - ATMEL Corporation |
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249 / 393 page  249 8018N–AVR–08/09 ATmega169P 23.5.4 LCDCCR – LCD Contrast Control Register • Bits 7:5 – LCDDC2:0: LDC Display Configuration The LCDDC2:0 bits determine the amount of time the LCD drivers are turned on for each volt- age transition on segment and common pins. A short drive time will lead to lower power consumption, but displays with high internal resistance may need longer drive time to achieve satisfactory contrast. Note that the drive time will never be longer than one half prescaled LCD clock period, even if the selected drive time is longer. When using static bias or blanking, drive time will always be one half prescaled LCD clock period. • Bit 4 – LCDMDT: LCD Maximum Drive Time Writing this bit to one turns the LCD drivers on 100% on the time, regardless of the drive time configured by LCDDC2:0. • Bits 3:0 – LCDCC3:0: LCD Contrast Control The LCDCC3:0 bits determine the maximum voltage V LCD on segment and common pins. The different selections are shown in Table 23-8. New values take effect every beginning of a new frame. Bit 765 4 321 0 (0xE7) LCDDC2 LCDDC1 LCDDC0 LCDMDT LCDCC3 LCDCC2 LCDCC1 LCDCC0 LCDCCR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Table 23-7. LCD Display Configuration LCDDC2 LCDDC1 LCDDC0 Nominal drive time 0 0 0 300 µs 001 70 µs 0 1 0 150 µs 0 1 1 450 µs 1 0 0 575 µs 1 0 1 850 µs 1 1 0 1150 µs 111 50% of clkLCD_PS |
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