ATmega169P datasheet(92/393 Pages) ATMEL

92 / 393 page

8018N–AVR–08/09

ATmega169P

The double buffered Output Compare Register (OCR0A) is compared with the Timer/Counter

value at all times. The result of the compare can be used by the Waveform Generator to gener-

ate a PWM or variable frequency output on the Output Compare pin (OC0A). See ”Output

Compare Unit” on page 93. for details. The compare match event will also set the Compare Flag

(OCF0A) which can be used to generate an Output Compare interrupt request.

14.2.2

Definitions

Many register and bit references in this section are written in general form. A lower case “n”

replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Com-

pare unit number, in this case unit A. However, when using the register or bit defines in a

program, the precise form must be used, i.e., TCNT0 for accessing Timer/Counter0 counter

value and so on.

The definitions in Table 14-1 are also used extensively throughout the document.

14.3

Timer/Counter Clock Sources

The Timer/Counter can be clocked by an internal or an external clock source. The clock source

is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits

located in the Timer/Counter Control Register (TCCR0A). For details on clock sources and pres-

caler, see ”Timer/Counter0 and Timer/Counter1 Prescalers” on page 135.

14.4

Counter Unit

The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure

14-2 shows a block diagram of the counter and its surroundings.

Figure 14-2. Counter Unit Block Diagram

Table 14-1.

Timer/Counter Definitions

BOTTOM

The counter reaches the BOTTOM when it becomes 0x00.

MAX

The counter reaches its MAXimum when it becomes 0xFF (decimal 255).

TOP

The counter reaches the TOP when it becomes equal to the highest value in the

count sequence. The TOP value can be assigned to be the fixed value 0xFF

(MAX) or the value stored in the OCR0A Register. The assignment is dependent

on the mode of operation.

DATA BUS

TCNTn

Control Logic

count

TOVn

(Int.Req.)

Clock Select

top

Edge

Detector

( From Prescaler )

clk

bottom

direction

clear

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