ATmega169P datasheet(248/393 Pages) ATMEL

248 / 393 page

248

8018N–AVR–08/09

ATmega169P

• Bit 3 – Res: Reserved Bit

This bit is reserved and will always read as zero.

• Bits 2:0 – LCDCD2:0: LCD Clock Divide 2, 1, and 0

The LCDCD2:0 bits determine division ratio in the clock divider. The various selections are

shown in Table 23-5 on page 248. This Clock Divider gives extra flexibility in frame rate

selection.

The frame frequency can be calculated by the following equation:

Where:

N = prescaler divider (16, 64, 128, 256, 512, 1024, 2048, or 4096).

K = 8 for duty = 1/4, 1/2, and static.

K = 6 for duty = 1/3.

D = Division factor (see Table 23-5).

This is a very flexible scheme, and users are encouraged to calculate their own table to investi-

gate the possible frame rates from the formula above. Note when using 1/3 duty the frame rate

is increased with 33% when Frame Rate Register is constant. Example of frame rate calculation

is shown in Table 23-6.

Table 23-5.

LCD Clock Divide

LCDCD2

LCDCD1

LCDCD0

Output from Prescaler

divided by (D):

clk

LCD = 32.768 kHz, N = 16, and

Duty = 1/4, gives a frame rate of:

000

256 Hz

001

128 Hz

85.3 Hz

011

64 Hz

51.2 Hz

42.7 Hz

36.6 Hz

111

32 Hz

Table 23-6.

Example of frame rate calculation

clk

LCD

duty

LCDCD2:0

Frame Rate

4 MHz

1/4

2048

011

4000000/(8*2048*4) = 61 Hz

4 MHz

1/3

2048

011

4000000/(6*2048*4) = 81 Hz

32.768 kHz

Static

000

32768/(8*16*1) = 256 Hz

32.768 kHz

1/2

100

32768/(8*16*5) = 51 Hz

fframe

fclk

LCD

KND

⋅⋅

()

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