ATmega169P datasheet(94/393 Pages) ATMEL

94 / 393 page

8018N–AVR–08/09

ATmega169P

Figure 14-3. Output Compare Unit, Block Diagram

The OCR0A Register is double buffered when using any of the Pulse Width Modulation (PWM)

modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buff-

ering is disabled. The double buffering synchronizes the update of the OCR0 Compare Register

to either top or bottom of the counting sequence. The synchronization prevents the occurrence

of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.

The OCR0A Register access may seem complex, but this is not case. When the double buffer-

ing is enabled, the CPU has access to the OCR0A Buffer Register, and if double buffering is

disabled the CPU will access the OCR0A directly.

14.5.1

Force Output Compare

In non-PWM waveform generation modes, the match output of the comparator can be forced by

writing a one to the Force Output Compare (FOC0A) bit. Forcing compare match will not set the

OCF0A Flag or reload/clear the timer, but the OC0A pin will be updated as if a real compare

match had occurred (the COM0A1:0 bits settings define whether the OC0A pin is set, cleared or

toggled).

14.5.2

Compare Match Blocking by TCNT0 Write

All CPU write operations to the TCNT0 Register will block any compare match that occur in the

next timer clock cycle, even when the timer is stopped. This feature allows OCR0A to be initial-

ized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is

enabled.

OCFnx (Int.Req.)

= (8-bit Comparator )

OCRnx

OCnx

DATA BUS

TCNTn

WGMn1:0

Waveform Generator

top

FOCn

COMnx1:0

bottom

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