ATmega328P datasheet(34/345 Pages) ATMEL

34 / 345 page

7810A–AVR–11/09

ATmega328P [Preliminary]

When applying an external clock, it is required to avoid sudden changes in the applied clock fre-

quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from

one clock cycle to the next can lead to unpredictable behavior. If changes of more than 2% is

required, ensure that the MCU is kept in Reset during the changes.

Note that the System Clock Prescaler can be used to implement run-time changes of the internal

clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” on page

34 for details.

8.9

Clock Output Buffer

The device can output the system clock on the CLKO pin. To enable the output, the CKOUT

Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other cir-

cuits on the system. The clock also will be output during reset, and the normal operation of I/O

pin will be overridden when the fuse is programmed. Any clock source, including the internal RC

Oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is

used, it is the divided system clock that is output.

8.10

Timer/Counter Oscillator

ATmega328P uses the same crystal oscillator for Low-frequency Oscillator and Timer/Counter

Oscillator. See “Low Frequency Crystal Oscillator” on page 31 for details on the oscillator and

crystal requirements.

ATmega328P share the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) with XTAL1 and

XTAL2. When using the Timer/Counter Oscillator, the system clock needs to be four times the

oscillator frequency. Due to this and the pin sharing, the Timer/Counter Oscillator can only be

used when the Calibrated Internal RC Oscillator is selected as system clock source.

Applying an external clock source to TOSC1 can be done if EXTCLK in the ASSR Register is

written to logic one. See “Asynchronous Operation of Timer/Counter2” on page 147 for further

description on selecting external clock as input instead of a 32.768 kHz watch crystal.

8.11

System Clock Prescaler

The ATmega328P has a system clock prescaler, and the system clock can be divided by setting

the “CLKPR – Clock Prescale Register” on page 357. This feature can be used to decrease the

system clock frequency and the power consumption when the requirement for processing power

is low. This can be used with all clock source options, and it will affect the clock frequency of the

CPU and all synchronous peripherals. clk

I/O, clkADC, clkCPU, and clkFLASH are divided by a factor

as shown in Table 28-4 on page 308.

When switching between prescaler settings, the System Clock Prescaler ensures that no

glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than

neither the clock frequency corresponding to the previous setting, nor the clock frequency corre-

sponding to the new setting. The ripple counter that implements the prescaler runs at the

frequency of the undivided clock, which may be faster than the CPU's clock frequency. Hence, it

is not possible to determine the state of the prescaler - even if it were readable, and the exact

time it takes to switch from one clock division to the other cannot be exactly predicted. From the

time the CLKPS values are written, it takes between T1 + T2 and T1 + 2 * T2 before the new

clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the pre-

vious clock period, and T2 is the period corresponding to the new prescaler setting.

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