MPC5604B datasheet(44/72 Pages) FREESCALE

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MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4

Electrical characteristics

Freescale Semiconductor

4.18.2

DSPI characteristics

Table 39. DSPI characteristics

No.

Symbol

Parameter

Value

Unit

Min

Typ

Max

tSCK

SR D SCK cycle time

—

fDSPI

SR D DSPI digital controller frequency

—

fCPU

MHz

—

Δt

CSC

CC D Internal delay between pad associated to SCK and

pad associated to CSn in master mode

—

1201

1 Maximum is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM pad.

tCSCext

2 The t

CSC delay value is configurable through a register. When configuring tCSC (using PCSSCK and CSSCK fields

in DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than

Δt

CSC to ensure

positive tCSCext.

CC D CS to SCK delay

Master mode

tCSCext = tCSC + ΔtCSC

SR D

Slave mode

—

tASCext

3 The t

ASC delay value is configurable through a register. When configuring tASC (using PASC and ASC fields in

DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than

Δt

ASC to ensure positive

tASCext.

CC D After SCK delay

Master mode

tASCext = tASC + ΔtCSC

SR D

Slave mode

1/fDSPI + 5 ns

—

tSDC

CC D SCK duty cycle

Master mode

—

tSCK/2

—

SR D

Slave mode

tSCK/2

—

SR D Slave access time

—

tDI

SR D Slave SOUT disable time

—

tSUI

SR D Data setup time for inputs

Master (MTFE = 0)

—

Slave

—

Master (MTFE = 1)

—

tHI

SR D Data hold time for inputs

Master (MTFE = 0)

—

Slave

4 This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of DSPI_MCR register.

—

Master (MTFE = 1)

—

tSUO

5 SCK and SOUT configured as MEDIUM pad

CC D Data valid after SCK edge

Master (MTFE = 0)

—

Slave

—

Master (MTFE = 1)

—

tHO

(5)

CC D Data hold time for outputs

Master (MTFE = 0)

—

Slave

5.5

—

Master (MTFE = 1)

—

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