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TVP3703 датащи(PDF) 17 Page - Texas Instruments |
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TVP3703 датащи(HTML) 17 Page - Texas Instruments |
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17 / 21 page ![]() TVP3703 VIDEO INTERFACE PALETTE TRUE-COLOR CMOS RAMDAC SLAS100 – MARCH 1996 17 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 operating characteristics DAC PARAMETER TVP3703-170 TVP3703-135 UNIT PARAMETER MIN TYP MAX MIN TYP MAX UNIT Resolution 8 8 bits DAC operating frequency 170 135 MHz Output current, black level pedestal (see Note 10) 0.95 1.44 1.9 0.95 1.44 1.9 mA Output current, white relative to black (see Note 10) 16.74 17.62 18.50 17.6 17.62 20.4 mA DAC-to-DAC matching (see Notes 10 and 11) ±2% ±5% ±2% ±5% EL Integral linearity error (see Note 10) ±1 ±1 LSB ED Differential linearity error (see Note 10) ±1 ±1 LSB DAC output compliance (see Note 10) –1 1.2 –1 1.2 V DAC output impedance 50 50 k Ω tr Rise time (black to white level) (see Notes 10, 12, and 13) 3 1 3 ns ts Settling time (black to white) (see Notes 10, 12, and 14) 5 10 ns Glitch energy (see Notes 10 and 12) 50 50 pVs Comparator trip voltage 340 340 mV Iref Reference input current 100 100 µA Internal reference voltage 1.235 1.235 V Internal reference voltage accuracy 1.15 1.235 1.27 1.15 1.235 1.27 V NOTES: 10. Vref = 1.235 V and RSET = 147 Ω 11. About the midpoint of the distribution of the three DACs 12. 37.5 Ω and 30 pF load 13. Measured between 10% and 90% of full scale transition. 14. Settling to within 2% of frame sync delay (fsd) timing diagrams tsu(SVL) th(LSX) td(RLQX) ta(RLQV) th(RHQX) td(RHQZ) tsu(DVWH) th(WHDX) WR, RD RS0 – RS2 D0 – D7 (Read) D0 – D7 (Write) trec(RHRL), trec(WHWL) tw(RLRH), tw(WLWH) Figure 1. Micro Port Read/Write Cycle Timing |
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