TVP3703

VIDEO INTERFACE PALETTE

TRUE-COLOR CMOS RAMDAC

SLAS100 – MARCH 1996

10

POST OFFICE BOX 655303

use of the hardware CRC feature (continued)

4.

Set BLANK high.

5.

Run for ten PCLK cycles.

6.

Set BLANK low.

7.

Run for 1200 dot clock cycles.

8.

Set 0x5555 on pixel bus input.

9.

Run for 20 PCLK cycles.

10. Set 0x0000 on the pixel bus input.

11. Run for three PCLK cycles.

12. Set bit 2 of the CRC test register to 0 and bit 1 to 1.

13. Wait for > 240 PCLK cycles.

14. Wait 1200 dot clock cycles.

15. Read the CRC low and high byte registers for the CRC result.

The CRC technique allows an authoritative check to be performed between the intended display and the actual

display at full video rates. For a given image (which can be an application’s image or a specially prepared test

screen), theoretically derived CRC values are calculated for each RGB color, which are then compared with the

TVP3703 hardware CRC values. Alternatively, the CRC value from a known good screen can be used as the

reference.

The CRC facility on the TVP3703 can be used to validate correct operation of:

The horizontal and vertical synchronization waveforms or timings do not affect hardware CRC accumulation.

Any discrepancy between the calculated and TVP3703 hardware accumulated CRC values indicates a problem

in the device or system being used.

The CRC logic on the TVP3703 is normally powered down. To perform a CRC test, bit 2 of the CRC test register

(index FFD6h) should be reset to 0 and returned to 1 afterwards to return to the default condition.

The CRC mechanism does not check the DAC outputs (i.e., what is physically being displayed on the monitor);

these can be tested using the TVP3703 SENSE output (generally readable as a register bit on the VGA

controller).

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