TVP3703 datasheet(8/21 Pages) TI

8 / 21 page

TVP3703

VIDEO INTERFACE PALETTE

TRUE-COLOR CMOS RAMDAC

SLAS100 – MARCH 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POWER MANAGEMENT REGISTER A (Index 0007h)

BIT

FUNCTION

RESET

VALUE

SLEEP

MODE†

Reserved (write 1)

Reserved (write 0)

1 = Power-down palette RAM

Reserved (write 0)

Reserved

2–0

Reserved (write 0)

† Indicates the effect of selecting sleep mode (the power management

POWER MANAGEMENT REGISTER B (Index 0008h)

BIT

FUNCTION

RESET

VALUE

7–3

Reserved

Not reset

1 = Power-down crystal oscillator

1 = Power-down VCLK generator

1 = Power-down MCLK generator

PLL PARAMETERS LOW REGISTERS

(Indexes 0020h, 0022h, . . . 0046h)

BIT

FUNCTION

RESET

VALUE

VCLK/MCLK source select 0 (see Table 4)

See Table 3

6–0

M value

See Table 3

PLL PARAMETERS HIGH REGISTERS

(Indexes 0021h, 0023h, . . . 0047h)

BIT

FUNCTION

RESET

VALUE

VCLK/MCLK source select 1 (see Table 4)

6–5

N2 value

See Table 3

4–0

N1 value

Table 4. VCLK/MCLK Source Select

(PLL parameters high and low registers – bit 7)

SOURCE

SELECT

SOURCE

SELECT

VCLK/MCLK FUNCTION

PLL

USED

fO +

) 2

(N1

) 2)

2N2

XIN

Yes‡

Reserved

O +

I XIN

2N2

fO = fI(XIN) direct

‡ See power management features section.

CLOCK SYNTHESIZER CONTROL REGISTER

(Index 0048h)

BIT

FUNCTION

RESET

VALUE

Reserved

0 = Select VCLK by terminals VS0 – VS3

1 = Select VCLK by bits 3 – 0

5–4

MCLK select (M0 – M3)

3–0

VCLK select (V0 – V15) if enabled by bit 6

CRC TEST REGISTER

(Index FFD6h)

BIT

VALUE

FUNCTION

RESET

VALUE

7–6

0 0

Blue selection

0 1

Green selection

Not reset

1 0

Red selection

Not reset

1 1

None selected

5–3

0 0 0

1 1 1

Bit 0 selected

Bit 7 selected

Not reset

→ 0

Transition initializes start of CRC

Use pixel bus input

Use self-test-generated patterns

Reserved

CRC LOW BYTE (Bits 7 – 0)

(Index FFD7h)

BIT

FUNCTION

RESET

VALUE

7– 0

Low byte of CRC value

Not reset

CRC HIGH BYTE (Bits 15 – 8)

(Index FFD8h)

BIT

FUNCTION

RESET

VALUE

7–0

High byte of CRC value

Not reset

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