TVP3703

VIDEO INTERFACE PALETTE

TRUE-COLOR CMOS RAMDAC

SLAS100 – MARCH 1996

9

POST OFFICE BOX 655303

programming the PLL clock generators

The conditions shown in the following equations must be followed when programming the PLL clock generators.

f

I XIN

10*6

2

* 2 v N1 v f

I XIN

10*6

* 2

(1)

(2)

(3)

Where:

0

v N1 v 31 and N1 must be an integer

64

106

f

I XIN

(N1

) 2) * 2 v M v 135

106

f

I XIN

(N1

) 2) * 2

Where:

0

v M v 127 and M must be an integer

2N2

+

f

I XIN

(M

) 2)

f

O

(N1

) 2)

Where:

0

v N2 v 3 and N2 must be integer

power management features

Two power reduction options are available on the TVP3703.

1.

Bit 0 of the pixel command register (sleep mode) provides a default power-down mode in which the following

sections of the device are powered down:

Micro port and palette-RAM power is maintained to allow read and write access to the internal registers or

2.

The power management register, located in the indexed register space (index 0007h), allows selective

power down of the device.

use of the hardware CRC feature

The TVP3703 hardware CRC feature supports testing of the entire pixel data path from the pixel port through

to the DAC inputs at full video rates up to 170 MHz on the TVP3703. Each of the three colors (red, green and

blue) are tested independently. CRCs are accumulated during active display, with accumulation being gated by

the BLANK signal.

A TVP3703 CRC can be accumulated in either active screen or self-test-pattern generation mode and is

controlled by bit 1 of the CRC test register (index FFD6h). To use the pattern generated CRC feature, perform

the following test procedure:

1.

Set the mode and verify the PIXMIX signal is low.

2.

Set the proper values in the CRC test register for the desired CRC mode. Set BLANK low. Wait for ten

PCLKS cycles.

3.

Set bit 2 of the CRC test register to 1 and bit 1 to 0.