TVP3703

VIDEO INTERFACE PALETTE

TRUE-COLOR CMOS RAMDAC

SLAS100 – MARCH 1996

5

POST OFFICE BOX 655303

direct RS access (continued)

Table 1. Direct RS Micro Port Accesses

RS(2–0)

VGA REGISTER

000

Address register (palette write)

001

Palette color value

010

Pixel mask/indirect access

011

Address register (palette read)

100

Index low byte

101

Indexed register

110

Pixel command register

111

Index high byte

indirect access

The indexed register space can also be accessed by a special mechanism of successive reads to the mask

register location 2h, as shown in Table 2. Reads from RS location 2h cause a state counter to be advanced by

one. Five successive reads of RS location 2h returns the mask register contents four times followed by the pixel

command register value.

If the indexed register space is not enabled, the next access is directed to the pixel mask (state 1 in Table 2).

States 3 to 4 require three reads from the pixel mask register and, when the pixel command register is written

to enable the indexed register space, the next access is again directed to the mask register (the next state after

state 5 is state 1).

The indirect access sequence can now enter states 6 and 7 to access the lower and higher byte of the index

register respectively. Subsequent reads or writes to location 2h access the register space pointed to by the index

register. After each indexed register access, the index register increments automatically. In this way, the entire

indexed register space can be moved as a block without the need to keep writing to the index register.

At any point in the above sequence, a read or write to any location other than 2h resets the state counter to

state 1.

On power up, the indirect access is truncated through the default setting of pixel command register bit 4 so that

the TVP3703 is identified by existing video basic input/output system (BIOS) code as a fast ATT20C490

RAMDAC.

Table 2. Indirect Access Sequence

CURRENT STATE†

NEXT STATE

STATE

REGISTER MAPPED

AT RS = 2h

READ FROM

RS = 2h AND INDEX

SPACE ENABLED

READ FROM

RS = 2h AND INDEX

SPACE DISABLED

(DEFAULT)

WRITE TO

RS = 2h

READ/WRITE TO

OTHER RS LOCATION

1

Pixel mask

2

2

1

1

2

Pixel mask

3

3

1

1

3

Pixel mask

4

4

1

1

4

Pixel mask

5

5

1

1

5

Pixel command

6

1

1

1

6

Index low byte

7

7

1

7

Index high byte

8

8

1

8

Indexed register

8‡

8‡

1

† Power-up state is state 1.

‡ Increment index register after access