TMS320VC5504 datasheet(63/128 Pages) TI

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6.3 Power Supplies

6.3.1

Power-Supply Sequencing

6.3.2

Power-Supply Design Considerations

6.3.3

Power-Supply Decoupling

TMS320VC5504

Fixed-Point Digital Signal Processor

www.ti.com

SPRS609A – JUNE 2009 – REVISED JULY 2009

The VC5504 includes four core voltag-level supplies (CVDD, CVDDRTC, USB_VDD1P3, USB_VDDA1P3), and

several I/O supplies (DVDDIO, DVDDEMIF, DVDDRTC, USB_VDDOSC, and USB_VDDA3P3), as well as several

analog supplies (ANA_LDOI, VDDA_PLL, VDDA_ANA, and USB_VDDPLL). To ensure proper device operation, a

specific power-up sequence must be followed. Some TI power-supply devices include features that

facilitate power sequencing—for example, Auto-Track and Slow-Start/Enable features. For more

information regarding TI's power management products and suggested devices to power TI DSPs, visit

www.ti.com/processorpower.

The VC5504 includes four core voltage-level supplies (CVDD, CVDDRTC, USB_VDD1P3, USB_VDDA1P3), and

several I/O supplies including—DVDDIO, DVDDEMIF, DVDDRTC, USB_VDDOSC, and USB_VDDA3P3

For proper device operation, the general power-up sequence requirements can be summarized as

ANA_LDOI and all core-level supplies must come up first, followed by the I/O level supplies. Specifically,

the power-up sequence requirement is:

1. Apply power to the ANA_LDOI, CVDDRTC, CVDD, USB_VDD1P3, USB_VDDA1P3, VDDA_ANA, and VDDA_PLL.

Note: the Analog LDO output (ANA_LDOO) can be used to power the VDDA_ANA, and VDDA_PLL

supplies.

2. Apply power to I/Os: DVDDIO, DVDDEMIF, DVDDRTC, USB_VDDOSC, USB_VDDA3P3, and USB_VDDPLL.

Core supplies must be powered before I/O supplies. If the I/O supplies are powered before the core

supply, the core signals controlling bi-directional I/Os are in an "undetermined state" and can set some of

the bi-directional I/Os to drive against an external device, causing bus contention. Therefore, the I/O

Supplies (DVDDIO, DVDDEMIF, DVDDRTC, USB_VDDOSC, USB_VDDA3P3, and USB_VDDPLL) should not ramp

above 1.65 V before core supplies (CVDDRTC, CVDD, USB_VDD1P3, USB_VDDA1P3) reach 0.9 V.

If the USB subsystem is not used, the USB Core (USB_VDD1P3, USB_VDDA1P3) and USB PHY and I/O level

supplies (USB_VDDOSC, USB_VDDA3P3, and USB_VDDPLL) can be powered on and off anytime after this

sequence. When powering on these supplies, the USB PHY, USB oscillator, and USB PLL (USB_VDDOSC,

USB_VDDA3P3, and USB_VDDPLL) should not ramp above 1.65 V before the USB Core (USB_VDD1P3,

USB_VDDA1P3) reaches 0.9 V. When powering off these supplies, the USB Core (USB_VDD1P3,

USB_VDDA1P3) should not drop below 0.9 V before the USB PHY, USB oscillator, and USB PLL

(USB_VDDOSC, USB_VDDA3P3, and USB_VDDPLL) drop below 1.65 V.

Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize

inductance and resistance in the power delivery path. Additionally, when designing for high-performance

applications utilizing the VC5504 device, the PC board should include separate power planes for core, I/O,

VDDA_ANA and VDDA_PLL (which can share the same PCB power plane), and ground; all bypassed with

high-quality low-ESL/ESR capacitors.

In order to properly decouple the supply planes from system noise, place capacitors (caps) as close as

possible to the VC5504. These caps need to be no more than 1.25 cm maximum distance from the

VC5504 power pins to be effective. Physically smaller caps, such as 0402, are better but need to be

evaluated from a yield/manufacturing point-of-view. Parasitic inductance limits the effectiveness of the

decoupling capacitors, therefore physically smaller capacitors should be used while maintaining the largest

available capacitance value.

Larger caps for each supply can be placed further away for bulk decoupling. Large bulk caps (on the order

of 10

µF) should be furthest away, but still as close as possible. Large caps for each supply should be

placed outside of the BGA footprint.

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