TMS320VC5504 datasheet(61/128 Pages) TI

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TMS320VC5504

Fixed-Point Digital Signal Processor

www.ti.com

SPRS609A – JUNE 2009 – REVISED JULY 2009

Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Temperature

(Unless Otherwise Noted) (continued)

PARAMETER

TEST CONDITIONS (1)

MIN

TYP

MAX

UNIT

Active, CVDD = 1.3 V, DSP clock = 100 MHz

Room Temp (25

°C), 75% DMAC + 25% ADD

0.22

mW/MHz

(typical sine wave data switching)

Active, CVDD = 1.05 V, DSP clock = 60 MHz

Room Temp (25

°C) , 75% DMAC + 25% ADD

0.15

mW/MHz

(typical data switching)

Active, CVDD = 1.3 V, DSP clock = 100 MHz

Room Temp (25

°C), 75% DMAC + 25% NOP

0.22

mW/MHz

(typical sine wave data switching)

Active, CVDD = 1.05 V, DSP clock = 60 MHz

Room Temp (25

°C) , 75% DMAC + 25% NOP

0.14

mW/MHz

(typical data switching)

Standby, CVDD = 1.3 V, Master clock disabled,

Room Temp (25

°C), DARAM and SARAM in active

0.44

mode

Core (CVDD) supply current

Standby, CVDD = 1.05 V, Master clock disabled,

ICDD

Room Temp (25

°C), DARAM and SARAM in active

0.26

mode

Standby, CVDD = 1.3 V, Master clock disabled,

Room Temp (25

°C), DARAM in retention and

0.40

SARAM in active mode

Standby, CVDD = 1.05 V, Master clock disabled,

Room Temp (25

°C), DARAM in retention and

0.23

SARAM in active mode

Standby, CVDD = 1.3 V, Master clock disabled,

Room Temp (25

°C), DARAM in active mode and

0.28

SARAM in retention

Standby, CVDD = 1.05 V, Master clock disabled,

Room Temp (25

°C), DARAM in active mode and

0.15

SARAM in retention

VDDA_PLL = 1.37 V

Analog PLL (VDDA_PLL) supply

Room Temp (25

°C), Phase detector = 170 kHz,

0.7

1.2

current

VCO = 120 MHz

Input capacitance

Output capacitance

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Device Operating Conditions

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