TMS320VC5504 datasheet(32/128 Pages) TI

32 / 128 page

TMS320VC5504

Fixed-Point Digital Signal Processor

SPRS609A – JUNE 2009 – REVISED JULY 2009

www.ti.com

Table 3-14. MMC1/SD Terminal Functions

SIGNAL

TYPE(1)

OTHER(2)(3)

DESCRIPTION

NAME

NO.

MMC/SD

This pin is multiplexed between MMC1, I2S1, and GPIO.

MMC1_CLK/

IPD

For MMC/SD, this is the MMC1 data clock output MMC1_CLK.

I2S1_CLK/

M13

DVDDIO

Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be

GP[6]

enabled or disabled via the PDINHIBR1 register.

This pin is multiplexed between MMC1, I2S1, and GPIO.

MMC1_CMD/

IPD

For MMC/SD, this is the MMC1 command I/O output MMC1_CMD.

I2S1_FS/

L14

DVDDIO

Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be

GP[7]

enabled or disabled via the PDINHIBR1 register.

MMC1_D3/

IPD

L13

I/O/Z

GP[11]

DVDDIO

The MMC1_D3 and MMC1_D2 pins are multiplexed between MMC1 and GPIO.

MMC1_D2/

IPD

K14

I/O/Z

The MMC1_D1 and MMC1_D0 pins are multiplexed between MMC1, I2S1, and

GP[10]

DVDDIO

GPIO.

MMC1_D1/

In MMC/SD mode, all these pins are the MMC1 nibble wide bi-directional data bus.

IPD

I2S1_RX/

M12

I/O/Z

Mux control via the SP1MODE bits in the EBSR.

DVDDIO

GP[9]

The IPD resistor on these pins can be enabled or disabled via the PDINHIBR1

MMC1_D0/

IPD

I2S1_DX/

M14

I/O/Z

DVDDIO

GP[8]

(1)

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

(2)

IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external

pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.

(3)

Specifies the operating I/O supply voltage for each signal

Table 3-15. MMC0/SD Terminal Functions

SIGNAL

TYPE(1)

OTHER(2)(3)

DESCRIPTION

NAME

NO.

MMC/SD

This pin is multiplexed between MMC0, I2S0, and GPIO.

MMC0_CLK/

IPD

For MMC/SD, this is the MMC0 data clock output MMC0_CLK.

I2S0_CLK/

L10

DVDDIO

Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be

GP[0]

enabled or disabled via the PDINHIBR1 register.

This pin is multiplexed between MMC0, I2S0, and GPIO.

MMC0_CMD/

IPD

For MMC/SD, this is the MMC0 command I/O output MMC0_CMD.

I2S0_FS/

M11

DVDDIO

Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be

GP[1]

enabled or disabled via the PDINHIBR1 register.

MMC0_D3/

IPD

L11

I/O/Z

GP[5]

DVDDIO

The MMC0_D3 and MMC0_D2 pins are multiplexed between MMC0 and GPIO.

MMC0_D2/

IPD

L12

I/O/Z

The MMC0_D1 and MMC0_D0 pins are multiplexed between MMC0, I2S0, and

GP[4]

DVDDIO

GPIO.

MMC0_D1/

In MMC/SD mode, these pins are the MMC0 nibble wide bi-directional data bus.

IPD

I2S0_RX/

M10

I/O/Z

Mux control via the SP0MODE bits in the EBSR.

DVDDIO

GP[3]

The IPD resistor on these pins can be enabled or disabled via the PDINHIBR1

MMC0_D0/

IPD

I2S0_DX/

I/O/Z

DVDDIO

GP[2]

(1)

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

(2)

IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external

pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.

(3)

Specifies the operating I/O supply voltage for each signal

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