TMS320VC5504 datasheet(49/128 Pages) TI

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4.5 Configurations at Reset

4.5.1

Device and Peripheral Configurations at Device Reset

4.6 Configurations After Reset

4.6.1

External Bus Selection Register (EBSR)

TMS320VC5504

Fixed-Point Digital Signal Processor

www.ti.com

SPRS609A – JUNE 2009 – REVISED JULY 2009

Some device configurations are determined at reset. The following subsections give more details.

Table 4-2 summarizes the device boot and configuration pins that are required to be statically tied high,

tied low, or left unconnected during device operation. For proper device operation, a device reset should

be initiated after changing any of these pin functions.

Table 4-2. Default Functions Affected by Device Configuration Pins

CONFIGURATION PINS

SIGNAL NO.

IPU/IPD

FUNCTIONAL DESCRIPTION

DSP_LDO_EN

D12

–

[Not supported on this device. Reserved for

compatibility with future devices]. For proper

device operation, this pin must be connected to

ground (VSS). For future device family pin

compatibility, board designs should have this pin

layout with a zero-

Ω resistor to ANA_LDOI and a

zero-

Ω resistor to ground. For VC5504, only the

zero-

Ω resistor to ground should be populated.

DSP_LDO_V

D13

–

[Not supported on this device. Reserved for

compatibility with future devices]. For proper

device operation, this pin must be connected to

the same supply as the ANA_LDOI pin (B12). For

future device family pin compatibility, board

designs should have this pin layout with a zero-

Ω

resistor to ANA_LDOI and a zero-

Ω resistor to

ground. For VC5504, only the zero-

Ω resistor to

ANA_LDOI should be populated.

CLK_SEL

–

Clock input select.

0 = 32-KHz on-chip oscillator drives the RTC

timer and the DSP clock generator while CLKIN

is ignored.

1 = CLKIN drives the DSP clock generator and

the 32-KHz on-chip oscillator drives only the RTC

timer.

This pin is not allowed to change during device

operation; it must be tied high or low at the

board.

For proper device operation, external pullup/pulldown resistors may be required on these device

configuration pins. For discussion situations where external pullup/pulldown resistors are required, see

Section 4.8.1, Pullup/Pulldown Resistors.

This device also has RESERVED pins that need to be configured correctly for proper device operation

(statically tied high, tied low, or left unconnected at all times). For more details on these pins, see

Table 3-18, Reserved and No Connects Terminal Functions.

The following sections provide details on configuring the device after reset. Multiplexed pin functions are

selected by software after reset. For more details on multiplexed pin function control, see Section 4.7,

Multiplexed Pin Configurations.

The External Bus Selection Register (EBSR) determines the mapping of the I2S2, I2S3, UART, SPI, and

GPIO signals to 21 signals of the external parallel port pins. It also determines the mapping of the I2S or

MMC/SD ports to serial port 1 pins and serial port 2 pins. The EBSR register is located at port address

0x1C00. Once the bit fields of this register are changed, the routing of the signals takes place on the next

CPU clock cycle.

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