THS0842

DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER

WITH SINGLE OR DUAL PARALLEL BUS OUTPUT

SLAS246 – DECEMBER 1999

3

POST OFFICE BOX 655303

ADC pipeline block diagram

SHA

DAC

ADC

+

–

ADC

Correction Logic

Output Buffers

22

2

2

2

D0(LSB)–D7(MSB)

2

2

SHA

SHA

SHA

SHA

SHA

The single-pipeline architecture uses 6 ADC/DAC stages and one final flash ADC. Each stage produces a

resolution of 2 bits. Digital correction logic generates its result using the 2-bit result from the first stage, 1 bit from

each of the 5 succeeding stages, and 1 bit from the final stage in order to arrive at an 8-bit result. The correction

logic ensures no missing codes over the full operating temperature range.

circuit diagrams of inputs and outputs

DVDD

AVDD

AVDD

0.5 pF

Internal

Reference

Generator

REFTO

or

REFBO

AVDD

REFBI

or

REFTI

OE

ALL DIGITAL INPUT CIRCUITS

AIN INPUT CIRCUIT

REFERENCE INPUT CIRCUIT

D0–D7 OUTPUT CIRCUIT

DRVDD

DRVSS

D_Out

D