THS0842

DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER

WITH SINGLE OR DUAL PARALLEL BUS OUTPUT

SLAS246 – DECEMBER 1999

27

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

THS0842

DA7

DA0

COUT

COUT

88

1D7

1D0

1Q7

1Q0

1D8

1D9

1Q8

1Q9

SN74LVC827A

SN74LVC374A

1D7

1D0

1Q7

1Q0

CLK

1D15

1D8

1Q15

1Q0

1D7

1D0

FIFO

HF Flag

WRTCLK

16

TMS320 DSP

INTR

Figure 27. Single Bus FIFO Connection to DSP Example

THS0842

DA7– DA0

FIFO

D16 – D9

D7 – D0

> WRTCLK

8

COUT

DSP

16

1Q15 – 1Q0

HF Flag

DB7– DB0

8

INTR

Figure 28. Dual Bus FIFO Connection to DSP Example

layout, decoupling and grounding rules

Proper grounding and layout of the PCB on which the THS0842 is populated are essential to achieve the stated

performance. It is advisable to use separate analog and digital ground planes that are spliced underneath the

device. The THS0842 has digital and analog terminals on opposite sides of the package to make this easier.

Since there is no internal connection between analog and digital grounds, they have to be joined on the PCB.

It is advisable to do this at one point in close proximity to the THS0842.

3 V instead of the nominal 3.3 V improves performance because of the lower switching noise caused by the

output buffers.

Because of the high sampling rate and switched-capacitor architecture, THS0842 generates transients on the

supply and reference lines. Proper decoupling of these lines is essential. Decoupling as shown in the schematic

of the THS0842 EVM is recommended.