THS0842

DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER

WITH SINGLE OR DUAL PARALLEL BUS OUTPUT

SLAS246 – DECEMBER 1999

19

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

analog input (continued)

To maintain the frequency performance outlined in the specifications, the total source impedance should be

R

S t

1

÷ 2f

CLK

C

I

In(256) –R

SW

The analog input of the THS0842 is a differential input that can be configured in various ways depending on

the signal source and the required level of performance. A fully differential connection (Figure 20) will deliver

the best performance from the converter. A dc voltage source, CML, equal to 1.5 V (typical), is made available

to the user to help simplify circuit design when using an ac coupled differential input. This low output impedance

voltage source is not designed to be a reference or to be loaded, but makes an excellent dc bias source and

stays well within the analog input common mode voltage range over temperature. Defining VREFD = VREFT

– VREFB, each single-ended analog input is limited to be between VCML + VREFD/2 and VCML – VREFD/2.

For the ac coupled differential input (Figure 23), full scale is achieved when the +I/Q and –I/Q input signals are

0.5 VPP, with –I/Q being 180 degrees out of phase with +I/Q. The converter will be at positive full scale when

the +I/Q input is at CML + 0.25 V and the –I/Q input is at CML – 0.25 V (+I/Q + I/Q – = 0.5 V). Conversely, the

converter will be at negative full scale when the +I/Q input is equal to CML – 0.25 V and –I/Q is at CML + 0.25 V

(I/Q+ + I/Q– = –0.5 V) (see Figure 19).