THS0842

DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER

WITH SINGLE OR DUAL PARALLEL BUS OUTPUT

SLAS246 – DECEMBER 1999

6

POST OFFICE BOX 655303

(unless otherwise noted)

power supply

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

AVDD

AV

DV

DRV

3 3 V

73

95

IDD

Operating supply current

DVDD

AVDD = DVDD = DRVDD = 3.3 V,

CL =15 pFVI = 1 MHz –1 dBFS

3

3.8

mA

DRVDD

CL = 15 F, VI = 1 MHz, –1 dBFS

17

22

PD

Power dissipation

PWDN_REF = L

320

393

PD

Power dissipation

PWDN_REF = H

275

335

mW

PD(STBY)

Standby power

STBY = H,

CLK held high or low

11

15

logic inputs

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

IIH

High-level input current on CLK†

AVDD = DVDD = DRVDD = CLK = 3.6 V

10

µA

IIL

Low-level input current on digital inputs

(OE, STDBY, PWDN_REF, CLK)

AVDD = DVDD = DRVDD = 3.6 V,

Digital inputs at 0 V

10

µA

CI

Input capacitance

5

pF

† IIH leakage current on other digital inputs (OE, STDBY, PWDN_REF) is not measured since these inputs have an internal pull-down resistor of

4 K

Ω to DGND.

logic outputs

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOH

High-level output voltage

AVDD = DVDD = DRVDD = 3 V at IOH = 50 µA,

Digital output forced high

2.8

V

VOL

Low-level output voltage

AVDD = DVDD = DRVDD = 3.6 V at IOL = 50 µA,

Digital output forced low

0.1

V

CO

Output capacitance

5

pF

IOZH

High-impedance state output current to

high level

AVDD =DVDD =DRVDD =3 6V

10

µA

IOZL

High-impedance state output current to

low level

AVDD = DVDD = DRVDD = 3.6 V

10

µA