THS0842

DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER

WITH SINGLE OR DUAL PARALLEL BUS OUTPUT

SLAS246 – DECEMBER 1999

25

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

digital inputs

The digital inputs are CLK, STDBY, PWDN_REF, and OE. All these signals, except CLK, have an internal

pulldown resistor to connect to digital ground. This provides a default active operation mode using internal

references when left unconnected.

The CLK signal at high frequencies should be considered as an analog input. Overshoot/undershoot should be

minimized by proper termination of the signal close to the THS0842. An important cause of performance

degradation for a high-speed ADC is clock jitter. Clock jitter causes uncertainty in the sampling instant of the

ADC, in addition to the inherent uncertainty on the sampling instant caused by the part itself, as specified by

formula shows the relation:

dtmax + 1 B p f2

N

)1

As an example, for an 8-bit converter with a 15-MHz input, the jitter needs to be kept <41 pS in order not to have

changes in the LSB of the ADC output due to the total aperture error.

digital outputs

The output of THS0842 is straight binary code. Capacitive loading on the output should be kept as low as

possible (a maximum loading of 10 pF is recommended) to provide best performance. Higher output loading

causes higher dynamic output currents and can increase noise coupling into the device analog front end. To

drive higher loads, use an output buffer is recommended. See Figure 25 through Figure 28 for examples.

When clocking output data from the THS0842, it is important to observe its timing relation to CLK. Pipeline ADC

delay is 55 clock cycles to which the maximum output propagation delay is added. See Note 6 in the specification

section for more details.