ANALOG INPUT

DIGITAL INTERFACE

TIMING AND CONTROL

READING DATA

READING THE DATA IN BYTE MODE

ADS7882

PRINCIPLES OF OPERATION (continued)

When the converter enters hold mode, the voltage difference between the +IN and -IN inputs is captured on the

internal capacitor array. The voltage on the –IN input is limited to between –0.2 V and 0.2 V, thus allowing the

input to reject a small signal which is common to both the +IN and -IN inputs. The +IN input has a range of –0.2

V to (+Vref +0.2 V). The input span (+IN – (–IN)) is limited from 0 V to VREF.

The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, signal

frequency, and source impedance. Essentially, the current into the ADS7882 charges the internal capacitor array

during the sample period. After this capacitance has been fully charged, there is no further input current (this

may not happen when a signal is moving continuously). The source of the analog input voltage must be able to

charge the input capacitance (27 pF) to better than a 12-bit settling level with a step input within the acquisition

time of the device. The step size can be selected equal to the maximum voltage difference between two

consecutive samples at the maximum signal frequency. (Refer to Figure 35 for the suggested input circuit.) When

the converter goes into hold mode, the input impedance is greater than 1 G

Ω.

Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, both

–IN and +IN inputs should be within the limits specified. Outside of these ranges, the converter's linearity may

not meet specifications.

Care should be taken to ensure that +IN and -IN see the same impedance to the respective sources. (For

example, both +IN and –IN are connected to a decoupling capacitor through a 21-

Ω resistor as shown in

Figure 35.) If this is not observed, the two inputs could have different settling times. This may result in an offset

error, gain error, or linearity error which changes with temperature and input voltage.

Refer to the SAMPLING AND CONVERSION START section and the CONVERSION ABORT section.

The ADS7882 outputs full parallel data in straight binary format as shown in Table 1. The parallel output is active

when CS and RD are both low. There is a minimal quiet sampling period requirement around the falling edge of

CONVST as stated in the timing requirements section. Data reads or bus three-state operations should not be

attempted within this period. Any other combination of CS and RD 3-states the parallel output. Refer to Table 1

for ideal output codes.

DESCRIPTION

ANALOG VALUE

BINARY CODE

HEX CODE

Full scale

1111 1111 1111

FFF

Midscale

1000 0000 0000

800

Midscale – 1 LSB

0111 1111 1111

7FF

Zero

0 V

0000 0000 0000

000

(1)

The output data appears as a full 12-bit word (D11–D0) on pins DB11–DB0 (MSB–LSB) if BYTE is low.

The result can also be read on an 8-bit bus for convenience by using pins DB11–DB4. In this case two reads are

necessary; the first as before, leaving BYTE low and reading the 8 most significant bits on pins DB11–DB4, and

then bringing BYTE high. When BYTE is high, the lower bits (D3–D0) followed by all zeros are on pins

DB11–DB4 (refer to Table 2).

These multi-word read operations can be performed with multiple active RD signals (toggling) or with RD tied low

for simplicity.

Copyright © 2008, Texas Instruments Incorporated

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