A_PWD

BUSY

SAMPLE

(Internal)

NAP

(Internal Active High)

Start section.

POWERDOWN/RESET

Power Down

Phase

1111 1110 0000

1

2

3

4

5

PWD/RST

BUSY

D11−D0

First 4 Invalid Conversions

Valid Conversions

RESET Phase

Invalid Data

Valid Data

1111 1110 0000

1

2

3

4

5

PWD/RST

BUSY

D11−D0

First 4 Invalid Conversions

Valid Conversions

RESET Phase

Invalid Data

Valid Data

45 ns

ADS7882

Figure 10. Device Operation While A_PWD is Toggling

A low level on the PWD/RST pin puts the device in the powerdown phase. This is an asynchronous signal. As

PWD/RST. During this period the output code is FE0 (hex) to indicate that the device is in the reset phase. The

the first four conversions after a power-up (see Figure 11) or an end of reset (see Figure 12). The device is

initialized during the first four conversions.

Figure 11. Device Power Down

Figure 12. Device Reset

12

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