CONVERSION ABORT

1111 1110 0000

CS

CONVST

BUSY

RD

D11−D0

DATA READ

D11−4 & D3−0

D3−0

CS

CONVST

BUSY

D11−D0

BYTE

RD

ADS7882

The falling edge of CS aborts the conversion while BUSY is high and CONVST is high (see Figure 4). The

device outputs FE0 (hex) to indicate a conversion abort.

Figure 4. Conversion Abort

Two conditions need to be satisfied for a read operation. Data appears on the D11 through D0 pins (with D11

MSB) when both CS and RD are low. Figure 5 and Figure 6 illustrate the device read operation. The bus is

3-stated if any one of the signals is high.

Figure 5. Read Control via CS and RD

There are two output formats available. Twelve bit data appears on the bus during a read operation while BYTE

is low. When BYTE is high, the lower byte (D3 through D0 followed by all zeroes) appears on the data bus with

D3 in the MSB. This feature is useful for interfacing with eight bit microprocessors and microcontrollers.

Copyright © 2008, Texas Instruments Incorporated

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