TIMING REQUIREMENTS

ADS7882

All specifications typical at –40°C to 85°C, +VA = +5 V, +VBD = +5 V

(1) (2) (3) (4)

PARAMETER

MIN

TYP

MAX

UNIT

REF FIG.

Conversion time

280

ns

5

Acquisition time

53

ns

5

SAMPLING AND CONVERSION START

Hold time CS low to CONVST high (with BUSY high)

10

ns

3

Delay CONVST high to acquisition start

2

4

5

ns

1

Hold time, CONVST high to CS high with BUSY low

10

ns

1

Hold time, CONVST low to CS high

10

ns

1

Delay CONVST low to BUSY high

40

ns

1

CS width for acquisition or conversion to start

20

ns

2

Delay CS low to acquisition start with CONVST high

2

4

5

ns

2

Pulse width, from CS low to CONVST low for acquisition to start

20

ns

2

Delay CS low to BUSY high with CONVST low

40

ns

2

25

ns

CONVERSION ABORT

Setup time CONVST high to CS low with BUSY high

15

ns

4

Delay time CS low to BUSY low with CONVST high

20

ns

4

DATA READ

Delay RD low to data valid with CS low

25

ns

Delay BYTE high to LSB word valid with CS and RD low

25

ns

5

Delay time RD high to data 3-state with CS low

25

ns

5

Delay time end of conversion to BUSY low

20

ns

5

Quiet sampling time RD high to CONVST low

20

ns

5

Delay CS low to data valid with RD low

25

ns

5

Delay CS high to data 3-state with RD low

25

ns

6

Quiet sampling time CS low to CONVST low

25

ns

6

BACK-TO-BACK CONVERSION

Delay BUSY low to data valid

10

ns

7, 8

Pulse width, CONVST high

63

ns

7, 8

Pulse width, CONVST low

20

ns

7

POWER DOWN/RESET

Pulse width, low for PWD/RST to reset the device

45

6140

ns

10

Pulse width, low for PWD/RST to power down the device

7200

ns

9

Delay time, power up after PWD/RST is high

25

ns

9

(1)

(2)

See timing diagram.

(3)

Quiet period before conversion start, no data bus activity including data bus 3-state is allowed in this period.

(4)

All timings are measured with 20 pF equivalent loads on all data bits and BUSY pin.

Copyright © 2008, Texas Instruments Incorporated

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