SH7018 datasheet(98/431 Pages) RENESAS

98 / 431 page

7.2.2

Bus Control Register 2 (BCR2)

BCR2 is a 16-bit read/write register that specifies the number of idle cycles and

CS signal assert

extension of each CS space.

BCR2 is initialized by power-on resets to H'FFFF.

Bit:

IW31

IW30

IW21

IW20

IW11

IW10

IW01

IW00

Initial value:

R/W:

R/W

Bit:

CW3

CW2

CW1

CW0

SW3

SW2

SW1

SW0

Initial value:

R/W:

R/W

• Bits 15 to 8—Idles between Cycles (IW31, IW30, IW21, IW20, IW11, IW10, IW01, IW00):

These bits specify idle cycles inserted between consecutive accesses when the second one is to

a different CS area after a read. Idles are used to prevent data conflict between ROM (and

other memories, which are slow to turn the read data buffer off), fast memories, and I/O

interfaces. Even when access is to the same area, idle cycles must be inserted when a read

access is followed immediately by a write access. The idle cycles to be inserted comply with

the area specification of the previous access

. Refer to section 7.4, Waits between Access

Cycles, for details.

IW31 and IW30 specify the idle between cycles for the CS3 space; IW21 and IW20 specify the

idle between cycles for the CS2 space; IW11 and IW10 specify the idle between cycles for the

CS1 space, and IW01 and IW00 specify the idle between cycles for the CS0 space.

Bit 15 (IW31)

Bit 14 (IW30)

Description

No idle cycle after accessing CS3 space

Inserts one idle cycle after accessing CS3

space

Inserts two idle cycles after accessing CS3

space

Inserts three idle cycles after accessing CS3

space

(Initial value)

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