H8S2245 datasheet(241/818 Pages) RENESAS

номер детали	H8S2245

подробное описание детали	Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series

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Section 7 Data Transfer Controller

Rev.3.00 Mar. 26, 2007 Page 199 of 772

REJ09B0355-0300

7.3.8

Chain Transfer

Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in

response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data

transfers, can be set independently.

Figure 7.9 shows the memory map for chain transfer. When activated, the DTC reads the register

information start address stored at the vector address, which corresponds to the activation request,

and then reads the first register information at that start address. After the data transfer, the CHNE

bit will be tested. When it has been set to 1, DTC reads the next register information located in a

consecutive area and performs the data transfer. These sequences are repeated until the CHNE bit

is cleared to 0.

Source

Destination

DTC vector

address

start address

CHNE = 1

CHNE = 0

Figure 7.9 Chain Transfer Memory Map

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