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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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H8S2245 датащи(PDF) 244 Page - Renesas Technology Corp |
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H8S2245 датащи(HTML) 244 Page - Renesas Technology Corp |
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244 / 818 page  Section 7 Data Transfer Controller Rev.3.00 Mar. 26, 2007 Page 202 of 772 REJ09B0355-0300 Table 7.9 Number of States Required for Each Execution Status Object to be Accessed On- Chip RAM On- Chip ROM On- Chip I/O Registers External Devices Bus width 32 16 8 16 8 16 Access states 112 22323 Vector read S I — 1 —— 46+2m 2 3+m Execution status Register information read/write S J 1 —— ————— Byte data read S K 112 22 3+m 2 3+m Word data read S K 114 24 6+2m 2 3+m Byte data write S L 112 22 3+m 2 3+m Word data write S L 114 24 6+2m 2 3+m Internal operation S M 1 m: Number of wait states in external device access The number of execution states is calculated from the formula below. Note that ∑ means the sum of all transfers activated by one activation event (the number in which the CHNE bit is set to 1, plus 1). Number of execution states = I · S I + ∑ (J · SJ + K · SK + L · SL) + M · SM For example, when the DTC vector address table is located in on-chip ROM, normal mode is set, and data is transferred from the on-chip ROM to an internal I/O register, the time required for the DTC operation is 13 states. The time from activation to the end of the data write is 10 states. |
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