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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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H8S2245 датащи(PDF) 239 Page - Renesas Technology Corp |
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H8S2245 датащи(HTML) 239 Page - Renesas Technology Corp |
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239 / 818 page  Section 7 Data Transfer Controller Rev.3.00 Mar. 26, 2007 Page 197 of 772 REJ09B0355-0300 7.3.7 Block Transfer Mode In block transfer mode, one operation transfers one block of data. A block area is specified for either the transfer source or the transfer destination. The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored. The other address register is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a CPU interrupt is requested. Table 7.7 lists the register information in block transfer mode and figure 7.8 shows memory mapping in block transfer mode. Table 7.7 Register Information in Block Transfer Mode Name Abbreviation Function DTC source address register SAR Designates source address DTC destination address register DAR Designates destination address DTC transfer count register AH CRAH Holds block size DTC transfer count register AL CRAL Block size count DTC transfer count register B CRB Transfer count |
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