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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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H8S2245 датащи(PDF) 56 Page - Renesas Technology Corp |
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H8S2245 датащи(HTML) 56 Page - Renesas Technology Corp |
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56 / 818 page  Section 1 Overview Rev.3.00 Mar. 26, 2007 Page 14 of 772 REJ09B0355-0300 Pin No. Type Symbol FP-100B, TFP-100B I/O Name and Function System control BACK 75 Output Bus request acknowledge: Indicates that the bus has been released to an external bus master. Interrupts NMI 63 Input Nonmaskable interrupt: Requests a nonmaskable interrupt. When this pin is not used, it should be fixed high. IRQ7 to IRQ0*1 94, 93, 13, 12, 73 to 76 Input Interrupt request 7 to 0: These pins request a maskable interrupt. Address bus A 23 to A 0 2, 1, 100, 99, 53 to 50, 48 to 41, 39 to 32 Output Address bus: These pins output an address. Data bus D 15 to D 0 30 to 19, 17 to 14 I/O Data bus: These pins constitute a bidirectional data bus. Bus control CS3 to CS0 94 to 97 Output Chip select: Signals for selecting areas 3 to 0. AS 70 Output Address strobe: When this pin is low, it indicates that address output on the address bus is enabled. RD 71 Output Read: When this pin is low, it indicates that the external address space can be read. HWR 72 Output High write: A strobe signal that writes to external space and indicates that the upper half (D 15 to D8) of the data bus is enabled. LWR 73 Output Low write: A strobe signal that writes to external space and indicates that the lower half (D 7 to D0) of the data bus is enabled. WAIT 74 Input Wait: Requests insertion of a wait state in the bus cycle when accessing external 3-state address space. |
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