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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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H8S2245 датащи(PDF) 172 Page - Renesas Technology Corp |
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H8S2245 датащи(HTML) 172 Page - Renesas Technology Corp |
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172 / 818 page  Section 5 Interrupt Controller Rev.3.00 Mar. 26, 2007 Page 130 of 772 REJ09B0355-0300 (2) Determination of Priority The DTC activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. See section 7.3.3, DTC Vector Table, for the respective priorities. (3) Operation Order If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception handling. Table 5.10 summarizes interrupt source selection and interrupt source clearance control according to the settings of the DTCE bit of DTCEA to DTCEF in the DTC and the DISEL bit of MRB in the DTC. Table 5.10 Interrupt Source Selection and Clearing Control Settings DTC Interrupt Source Selection/Clearing Control DTCE DISEL DTC CPU 0 * X 10 X 1 Legend: : The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt handling routine.) : The relevant interrupt is used. The interrupt source is not cleared. X : The relevant bit cannot be used. * : Don't care (4) Usage Note SCI and A/D converter interrupt sources are cleared when the appropriate DTC register is read or written to, and are independent of the DISEL bit. |
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