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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M32C/8A датащи(PDF) 238 Page - Renesas Technology Corp |
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M32C/8A датащи(HTML) 238 Page - Renesas Technology Corp |
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238 / 372 page  M32C/8A Group 17. Serial Interfaces Rev.1.00 Jul 15, 2007 Page 221 of 352 REJ09B0385-0100 17.1.2.1 Baud Rate In UART mode, the baud rate is the frequency of the clock divided by the setting value of the UiBRG register (i = 0 to 4) and again divided by 16. Table 17.5 lists an example of baud rate setting. Table 17.5 Baud Rate 17.1.2.2 LSB First or MSB First As shown in Figure 17.20, the UFORM bit in the UiC0 register (i = 0 to 4) determines a bit order. This function can be used when data length is 8 bits long. Figure 17.20 Bit Order Target Baud Rate (bps) UiBRG Count Source Peripheral Clock: 16MHz Peripheral Clock: 24MHz Peripheral Clock: 32MHz UiBRG Setting Value: n Actual Baud Rate (bps) UiBRG Setting Value: n Actual Baud Rate (bps) UiBRG Setting Value: n Actual Baud Rate (bps) 1200 f8 103(67h) 1202 155(9Bh) 1202 207(CFh) 1202 2400 f8 51(33h) 2404 77(4Dh) 2404 103(67h) 2404 4800 f8 25(19h) 4808 38(26h) 4808 51(33h) 4808 9600 f1 103(67h) 9615 155(9Bh) 9615 207(CFh) 9615 14400 f1 68(44h) 14493 103(67h) 14423 138(8Ah) 14388 19200 f1 51(33h) 19231 77(4Dh) 19231 103(67h) 19231 28800 f1 34(22h) 28571 51(33h) 28846 68(44h) 28986 31250 f1 31(1Fh) 31250 47(2Fh) 31250 63(3Fh) 31250 38400 f1 25(19h) 38462 38(26h) 38462 51(33h) 38462 51200 f1 19(13h) 50000 28(1Ch) 51724 38(26h) 51282 Actual baud rate = UiBRG register count source 16 × (UiBRG register setting value + 1) (1) When the UFORM bit in the UiC0 register (i = 0 to 4) is set to 0 (LSB first) ST D0 D2 D3 D4 D5 SP D1 (2) When the UFORM bit is set to 1 (MSB first) TXDi RXDi The above applies under the following conditions: - UiC0 register: CKPOL bit = 0 (transmit data output at the falling edge and receive data input at the rising edge of the serial clock) - UiC1 register: UiLCH bit = 0 (not inverted) and the UiLCH bit in the UiC1 register is set to 0 (not inverted). ST: Start bit P: Parity bit SP: Stop bit D6 D7 P ST D0 D2 D3 D4 D5 SP D1 D6 D7 P ST D7 D5 D4 D3 D2 SP D6 TXDi RXDi D1 D0 P ST SP P D7 D5 D4 D3 D2 D6 D1 D0 "H" "L" "H" "L" "H" "L" "H" "L" |
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