M32CSLASH8A datasheet(237/372 Pages) RENESAS

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M32C/8A Group

17. Serial Interfaces

Rev.1.00

Jul 15, 2007

Page 220 of 352

REJ09B0385-0100

Figure 17.19

Receive Operation in UART Mode

RXDi input

Start bit

Stop bit

Verify the level

(note 2)

Clock divided by UiBRG

Input the

receive data

“H”

“L”

(note 1)

Internal receive clock

IR bit in the SiRIC register

RI bit in the UiC1 register

RTSi output

“H”

“L”

i = 0 to 4

The above applies under the following conditions:

- UiMR register: STPS bit = 0 (1 stop bit)

- UiC0 register: CRS bit = 1 (CTS function not used)

NOTES:

1. RXDi input is sampled using the clock divided by the setting value of the UiBRG register. The internal receive

clock is generated after detecting the falling edge of the start bit, and then the receive operation starts.

2. When "L" is detected, the receive operation continues. When "H" is detected, the receive operation is cancelled.

When the receive operatin is cancelled, the RTSi output becomes "L".

Example of the receive operation timing (1 stop bit)

This bit becomes 1 when the data is transferred

from UARTi receive shift register to UiRB register

Set to 0 by an interrupt request

acknowledgement or by program

The RI bit becomes 0 and RTSi output

becomes "L" by reading the UiRB register

The output signal becomes "L"

when the RE bit in the UiC1 register

is set to 1

The output signal becomes "H"

when the receive operation starts

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