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M32C/8A датащи(PDF) 198 Page - Renesas Technology Corp |
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M32C/8A датащи(HTML) 198 Page - Renesas Technology Corp |
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198 / 372 page ![]() M32C/8A Group 16. Three-Phase Motor Control Timer Function Rev.1.00 Jul 15, 2007 Page 181 of 352 REJ09B0385-0100 Figure 16.3 INVC1 Register b7 b6 b5 b4 b1 b2 b3 Three-Phase PWM Control Register 1(1) Symbol INVC1 Address 0309h Bit Symbol Bit Name RW After Reset 00h b0 Function INV10 RW RW 0: Timer B2 underflow 1: Timer B2 underflow and a write to the TB2 register Timers A1, A2, and A4 start trigger select bit INV11 Timers A11, A21, and A41 control bit 0: Timers A11, A21, and A41 not used (Three-phase mode 0) 1: Timers A11, A21, and A41 used (Three-phase mode 1) INV12 Dead time timer count source (fDT) select bit 0: f1 1: f1 divided by 2 Dead time timer trigger select bit 0: Falling edge of one-shot pulse of timer (A4, A1, and A2(3)) 1: Rising edge of the three-phase output shift register (U-, V-, W-phase) INV16 RW 0 RO INV13 Carrier wave rise/fall detect flag(2) 0: Timer B2 underflow occurred an even number of times 1: Timer B2 underflow occurred an odd number of times INV14 Active level control bit 0: Active Low 1: Active High RW NOTES: 1. Set the INVC1 register after the PRC1 bit in the PRCR register is set to 1 (write enable). Set the INVC1 register while timers A1, A2, A4, and B2 are stopped. 2. The INV13 bit is enabled only when the INV06 bit is set to 0 (triangular wave modulation mode) and the INV11 bit to 1. 3. If the following conditions are all met, set the INV16 bit to 1. - The INV15 bit is set to 0 - Bits Dij (i = U, V or W, j = 0, 1) and DiBj in the IDBj register always have different values when the INV03 bit in the INVC0 register is set to 1 (three-phase control timer output enabled). (The upper arm and lower arm always output opposite level signals at any time except dead time.) If any of the above conditions is not met, set the INV16 bit to 0. RW − (b7) Reserved bit Set to 0 RW INV15 Dead time disable bit 0: Dead time enabled 1: Dead time disabled RW |
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