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M32C/8A датащи(PDF) 190 Page - Renesas Technology Corp |
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M32C/8A датащи(HTML) 190 Page - Renesas Technology Corp |
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190 / 372 page ![]() M32C/8A Group 15. Timers (Timer B) Rev.1.00 Jul 15, 2007 Page 173 of 352 REJ09B0385-0100 15.2.1 Timer Mode In timer mode, the timer counts an internally generated count source. Table 15.9 lists specifications of timer mode. Figure 15.27 shows a timer mode operation (Timer B). Table 15.9 Specifications of Timer Mode NOTES: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. Wait for one count source cycle or more to write after the count starts. Figure 15.27 Operation in Timer Mode (Timer B) Item Specification Count source f1, f8, f2n(1), fC32 Count operation • Counter decrements When the timer underflows, the contents of the reload register are reloaded into the counter and the count continues. Counter cycle n + 1 fj: count source frequency fj n: setting value of the TBi register (i=0 to 5), 0000h to FFFFh Count start condition The TBiS bit in the TABSR or TBSR register is set to 1 (count starts) Count stop condition The TBiS bit is set to 0 (count stops) Interrupt request generation timing When the timer underflows TBiIN pin function Programmable I/O port Read from timer A read from the TBi register returns a counter value. Write to timer • A write to the TBi register while the count is stopped: The value is written to both the reload register and the counter. • A write to the TBi register while counting: The value is written to the reload register (It is transferred to the counter at the next reload timing).(2) Count starts FFFFh n Count stops i = 0 to 5 (Condition) TBiMR register: Bits TMOD1 and TMOD0 are set to 00b (timer mode). TBiS bit in the TABSR or TBSR register Contents of the counter n = contents of the reload register 0000h IR bit in the TBiIC register 0 1 Underflow Reload Underflow Reload 0 1 Set to 0 by an interrupt request acknowledged or by program Count resumes |
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