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M16C/29 датащи(PDF) 309 Page - Renesas Technology Corp |
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M16C/29 датащи(HTML) 309 Page - Renesas Technology Corp |
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309 / 499 page ![]() 16. MULTI-MASTER I2C bus INTERFACE p u o r G 9 2 / C 6 1 M page 285 8 5 4 f o 7 0 0 2 , 0 3 .r a M 2 1 . 1 . v e R 2 1 1 0 - 1 0 1 0 B 9 0 J E R Figure 16.21 The bit reset timing (The STOP condition detection) Figure 16.22 The bit reset timing (The START condition detection) MST TRX BB flag SDA SCL Bit reset signal Related bits 1.5 VIIC cycle BB flag SDA SCL Bit reset signal BC2 - BC0 TRX (in slave mode) Related bits Figure 16.23 Bit set/reset timing ( at the completion of data transfer) SCL Bit set signal 1VIIC cycle PIN bit 2VIIC cycle Bit reset signal BC0 - BC2 MST(When in arbitration lost) TRX(When in NACK receive in slave transmit mode) The bits referring to reset TRX(ALS=0 meanwhile the slave receive R/W bit = 1 The bits referring to set |
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