M16CSLASH29 datasheet(271/499 Pages) RENESAS

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15. A/D Converter

page 247

NOTES:

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1. Do not generate the next ADTRG pin falling edge after the AN1 pin conversion is started until all selected pins

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complete A/D conversion. When an ADTRG pin falling edge is generated again during A/D conversion, its trigger

___________

is ignored. The falling edge of ADTRG pin, which was input after all selected pins complete A/D conversion, is

considered to be the next AN0 pin conversion start condition.

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2. The ADTRG pin falling edge is detected synchronized with the operation clock fAD. Therefore, when the ADTRG pin

___________

falling edge is generated in shorter periods than fAD, the second ADTRG pin falling edge may not be detected. Do

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not generate the ADTRG pin falling edge in shorter periods than fAD.

3. Do not write 1 (A/D conversion started) to the ADST bit in delayed trigger mode 1. When write 1,unexpected

interrupts may be generated.

4. AN00 to AN07, AN 20 to AN27, and AN30 to AN32 can be used in the same way as AN0 to AN7. However, all input

pins need to belong to the same group.

15.1.8 Delayed Trigger Mode 1

In delayed trigger mode 1, analog voltages applied to the selected pins are converted one-by-one to a

___________

digital code. When the input of the ADTRG pin (falling edge) changes state from “H” to “L”, a single sweep

conversion is started. After completing the AN0 pin conversion, the AN1 pin is not sampled and converted

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until the second ADTRG pin falling edge is generated. When the second ADTRG falling edge is generated,

the single sweep conversion of the pins after the AN1 pin is restarted. Table 15.12 shows the delayed

trigger mode 1 specifications. Figure 15.24 shows the operation example of delayed trigger mode 1.

Figure 15.25

and 15.26 show each flag operation in the ADSTAT0 register that corresponds to the

operation example. Figure 15.27 shows registers ADCON0 to ADCON2 in delayed trigger mode 1.

Figure 15.28

shows the ADTRGCON register in delayed trigger mode 1. Table 15.13 shows the trigger

select bit setting in delayed trigger mode 1.

Table 15.12 Delayed Trigger Mode 1 Specifications

Item

Specification

Function

Bits SCAN1 and SCAN0 in the ADCON1 register and bits ADGSEL1 and ADGSEL0

in the ADCON2 register select pins. Analog voltages applied to the selected

___________

pins are converted one-by-one to a digital code. At this time, the

ADTRG pin

___________

falling edge starts AN0 pin conversion and the second

ADTRG pin falling edge

starts conversion of the pins after AN1 pin

A/D Conversion Start

AN0 pin conversion start condition

Condition

___________

The ADTRG pin input changes state from “H” to “L” (falling edge) (1)

AN1 pin conversion start condition (2)

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The ADTRG pin input changes state from “H” to “L” (falling edge)

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•When the second ADTRG pin falling edge is generated during A/D conversion of

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the AN0 pin, input voltage of AN1 pin is sampled or after at the time of ADTRG

falling edge. The conversion of AN1 and the rest of the sweep starts when AN0

conversion is completed.

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•When the ADTRG pin falling edge is generated again during single sweep

conversion of pins after the AN1 pin, the conversion is not affected

A/D Conversion Stop

•A/D conversion completed

Condition

•Set the ADST bit to 0 (A/D conversion halted) (3)

Interrupt Request

Single sweep conversion completed

Generation Timing

Analog Input Pin

Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins)

and AN0 to AN7 (8 pins) (4)

Readout of A/D Conversion Result Readout one of registers AN0 to AN7 that corresponds to the selected pins

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