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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M16C/29 датащи(PDF) 215 Page - Renesas Technology Corp |
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M16C/29 датащи(HTML) 215 Page - Renesas Technology Corp |
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215 / 499 page  14. Serial I/O p u o r G 9 2 / C 6 1 M page 191 8 5 4 f o 7 0 0 2 , 0 3 .r a M 2 1 . 1 . v e R 2 1 1 0 - 1 0 1 0 B 9 0 J E R Figure 14.16 Typical transmit timing in UART mode (UART0, UART1) Start bit Parity bit TxDi CTSi 1 0 1 “L” “H” 0 1 0 1 TxDi 0 1 0 1 0 1 Transfer clock Tc 0 1 Tc Transfer clock D0 D1 D2 D3 D4 D5 D6 D7 ST PD0 D1 D2 D3 D4 D5 D6 D7 SP ST P SP D0 D1 ST Stop bit Start bit The transfer clock stops momentarily as CTSi is “H” when the stop bit is checked. The transfer clock starts as the transfer starts immediately CTSi changes to “L”. D0 D1 D2 D3 D4 D5 D6 D7 ST SP D8 D0 D1 D2 D3 D4 D5 D6 D7 ST D8 D0 D1 ST SPSP Stop bit Stop bit 0 SP Stopped pulsing because the TE bit = “0” Write data to the UiTB register UiC1 register TE bit UiC1 register TI bit UiC0 register TXEPT bit SiTIC register IR bit Transferred from UiTB register to UARTi transmit register The above timing diagram applies to the case where the register bits are set as follows: • Set the PRYE bit in the UiMR register to 1 (parity enabled) • Set the STPS bit in the UiMR register to 0 (1 stop bit) • Set the CRD bit in the UiC0 register to 0 (CTS/RTS enabled), the CRS bit to 0 (CTS selected). • Set the UiIRS bit to 1 (an interrupt request occurs when transmit completed): U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON register bit 1, and U2IRS bit is the U2C1 register bit 4 Cleared to 0 when interrupt request is accepted, or cleared to 0 by program UiC1 register TE bit UiC1 register TI bit UiC0 register TXEPT bit SiTIC register IR bit Cleared to 0 when interrupt request is accepted, or cleared to 0 by program Write data to the UiTB register Transferred from UiTB register to UARTi transmit register The above timing diagram applies to the case where the register bits are set as follows: • Set the PRYE bit in the UiMR register to 0 (parity disabled) • Set the STPS bit in the UiMR register to 1 (2 stop bits) • Set the CRD bit in the UiC0 register to 1 (CTS/RTS disabled) • Set the UiIRS bit to 0 (an interrupt request occurs when transmit buffer becomes empty): U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON register bit 1, and U2IRS bit is the U2C1 register bit 4 • Example of transmit timing when transfer data is 9-bit long (parity disabled, two stop bits) • Example of transmit timing when transfer data is 8-bit long (parity enabled, one stop bit) Tc = 16 (n + 1) / fj or 16 (n + 1) / fEXT fj: frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO) fEXT: frequency of UiBRG count source (external clock) n: value set to UiBRG i = 0 to 2 Tc = 16 (n + 1) / fj or 16 (n + 1) / fEXT fj: frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO) fEXT: frequency of UiBRG count source (external clock) n: value set to UiBRG i = 0 to 2 |
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